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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B04361-GM

Name: SI5338A-B04361-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B04361-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B04361-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B04361-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338A-B04361-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output. It delivers four independent differential or single-ended clocks (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) across 0.16–710 MHz, supports PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package for FPGA and processor clocking applications.

For engineers reviewing the SI5338A-B04361-GM datasheet, SI5338A-B04361-GM pinout, SI5338A-B04361-GM application, or SI5338A-B04361-GM equivalent, key selection criteria include its 0.7 ps RMS phase jitter (typ), independent output voltage per driver (1.5–3.3 V), flexible reference inputs (crystal, CMOS, differential up to 710 MHz), and glitchless 1 ppm frequency increment/decrement capability.

Technical Context

The SI5338A-B04361-GM integrates a two-stage PLL architecture: a high-performance integer-N PLL (Stage 1) locks to an external reference, followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each MultiSynth™ block supports integer or fractional mode operation with <20 ps programmable phase step resolution and 1 ppm frequency step accuracy.

Its output stage provides configurable drive strength, signal format, and supply voltage per channel (VDDO0–VDDO3), enabling simultaneous LVPECL (0.16–710 MHz), HCSL (0.16–250 MHz), and CMOS (0.16–200 MHz) outputs. The device includes loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation rate) on any output.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical over 12 kHz–20 MHz - meets PCIe Gen 3 SRNS and GbE jitter requirements
Output Frequency Range	0.16–710 MHz per channel - supports PCIe 100 MHz, Ethernet 125 MHz, and Fibre Channel 1.0625 GHz (via Fvco/4)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system clock sourcing
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V - simplifies mixed-voltage board design
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - space-efficient for high-density timing solutions
Operating Temperature	–40 °C to +85 °C - qualified for industrial and telecom line card environments
Power Consumption	45 mA core current typical at 100 MHz on all outputs - low-power operation without sacrificing jitter performance

Pinout & Package

The SI5338A-B04361-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are standardized across the Si5338 family and validated per Skyworks Rev. 1.6 datasheet (page 33).

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential reference inputs	Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination
IN3/IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); tolerate 0.7×VDD to 3.73 V input swing
CLK0A/CLK0B – CLK3A/CLK3B	Differential clock outputs	Four independent pairs; each configurable as LVPECL, LVDS, HCSL, or CML with per-channel VDDO
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output pair - enables mixed-signal interface without level shifters
SCL/SDA	I²C configuration interface	SMBus-compatible serial bus (up to 400 kHz) for runtime reprogramming and status monitoring
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent, any-frequency synthesizers with true zero ppm accuracy per output - eliminates need for multiple crystals
PCIe Gen 3 SRNS compliance	0.11–0.32 ps RMS jitter in Separate Reference No Spread mode - satisfies stringent PCIe 3.0 clocking requirements
Independent phase adjustment	<20 ps step resolution per output - enables precise skew alignment for multi-lane SerDes interfaces
Glitchless frequency tuning	1 ppm incremental/decremental steps via PINC/FDEC pins or I²C - allows dynamic clock rate adaptation without output interruption
Flexible spread spectrum	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output - reduces EMI in noise-sensitive systems

Applications

PCIe Gen 4 Switch Fabric	Ethernet 10GbE Line Card
Use Scenario: High-speed switch ASIC requiring synchronized 100 MHz common clock across multiple PCIe lanes with sub-0.5 ps RMS jitter. IC Role / Device Role / Timing Role: Primary clock generator delivering four identical 100 MHz HCSL clocks with Gen 4 Common Clock compliance. Use Value: Meets Intel's PCIe Gen 4 jitter spec (0.15–0.45 ps RMS) without external jitter cleaners, reducing BOM count and layout complexity.	Use Scenario: 10GbE PHY and MAC interface needing 156.25 MHz and 312.5 MHz clocks with tight inter-channel skew. IC Role / Device Role / Timing Role: Dual-frequency source providing 156.25 MHz LVDS and 312.5 MHz LVPECL outputs from a single crystal reference. Use Value: Eliminates separate oscillators and buffer ICs while maintaining <100 ps output-to-output skew across frequencies.
Broadcast Video Timing	FPGA-Based Test Equipment
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing platform requiring 297 MHz and 594 MHz pixel clocks with ultra-low deterministic jitter. IC Role / Device Role / Timing Role: Precision clock synthesizer generating 297 MHz LVDS and 594 MHz HCSL outputs with integer-mode MultiSynth™ to minimize DJ. Use Value: Achieves <2 ps pk-pk deterministic jitter (DJ) in integer mode - critical for error-free 12G-SDI serialization.	Use Scenario: Automated test system using FPGA fabric with multiple clock domains (100 MHz logic, 200 MHz ADC sampling, 500 MHz DAC reconstruction). IC Role / Device Role / Timing Role: Single-chip quad-clock source delivering three distinct frequencies with independent voltage and format control. Use Value: Reduces PCB layer count by consolidating clock generation and eliminating discrete level translators for mixed-voltage FPGA I/O banks.

PCIe Gen 4 Switch Fabric

Ethernet 10GbE Line Card

Use Scenario: High-speed switch ASIC requiring synchronized 100 MHz common clock across multiple PCIe lanes with sub-0.5 ps RMS jitter.

IC Role / Device Role / Timing Role: Primary clock generator delivering four identical 100 MHz HCSL clocks with Gen 4 Common Clock compliance.

Use Value: Meets Intel's PCIe Gen 4 jitter spec (0.15–0.45 ps RMS) without external jitter cleaners, reducing BOM count and layout complexity.

Use Scenario: 10GbE PHY and MAC interface needing 156.25 MHz and 312.5 MHz clocks with tight inter-channel skew.

IC Role / Device Role / Timing Role: Dual-frequency source providing 156.25 MHz LVDS and 312.5 MHz LVPECL outputs from a single crystal reference.

Use Value: Eliminates separate oscillators and buffer ICs while maintaining <100 ps output-to-output skew across frequencies.

Broadcast Video Timing

FPGA-Based Test Equipment

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing platform requiring 297 MHz and 594 MHz pixel clocks with ultra-low deterministic jitter.

IC Role / Device Role / Timing Role: Precision clock synthesizer generating 297 MHz LVDS and 594 MHz HCSL outputs with integer-mode MultiSynth™ to minimize DJ.

Use Value: Achieves <2 ps pk-pk deterministic jitter (DJ) in integer mode - critical for error-free 12G-SDI serialization.

Use Scenario: Automated test system using FPGA fabric with multiple clock domains (100 MHz logic, 200 MHz ADC sampling, 500 MHz DAC reconstruction).

IC Role / Device Role / Timing Role: Single-chip quad-clock source delivering three distinct frequencies with independent voltage and format control.

Use Value: Reduces PCB layer count by consolidating clock generation and eliminating discrete level translators for mixed-voltage FPGA I/O banks.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06181-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated crystal option; larger 5 × 5 mm 32-QFN package	Targets higher-channel-count systems (e.g., 8-lane PCIe Gen 5, multi-port 100GbE); requires more board area	Select when >4 outputs or sub-0.4 ps jitter is required; not drop-in compatible due to pin count and footprint change
ICS853S01AG-01	Fixed-frequency, non-programmable quad LVDS buffer; no synthesis capability; 0.6 ps RMS jitter; 32-pin TQFP	Limited to static clock fanout; cannot replace crystals or translate frequencies; lacks I²C control and alarms	Choose only for simple clock distribution where frequency flexibility and diagnostics are unnecessary

Compared with Si5332A-D06181-GM, the SI5338A-B04361-GM offers smaller footprint and lower cost for 4-output designs, while ICS853S01AG-01 provides lower jitter only in fixed-frequency buffer mode but no synthesis or configurability.

Availability

SI5338A-B04361-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch fabrics, 10GbE line cards, broadcast video timing systems, and FPGA-based test equipment requiring stable component supply and long-term lifecycle support.

Supply support for SI5338A-B04361-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with broad manufacturing scale and automotive-grade reliability.

The Si5338 product line was designed for high-performance, multi-protocol clock generation in datacenter, telecom, and broadcast systems-enabling consolidation of discrete oscillators into a single programmable IC with PCIe, Ethernet, and SONET/SDH compliance.

FAQ

What reference clock sources does the SI5338A-B04361-GM support?

The SI5338A-B04361-GM supports external crystal (8–30 MHz), single-ended CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential inputs (5–710 MHz). It accepts both AC-coupled differential references on IN1/IN2 and IN5/IN6, and DC-coupled single-ended signals on IN3/IN4. All references feed the same PLL stage, and the SI5338A-B04361-GM automatically detects and locks to the active input.

Does the SI5338A-B04361-GM meet PCIe Gen 4 Common Clock specifications?

Yes, the SI5338A-B04361-GM meets PCIe Gen 4 Common Clock jitter requirements with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines. This compliance is verified using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4, with all outputs in 100 MHz HCSL format and PLL bandwidth set to 2–5 MHz.

Can the SI5338A-B04361-GM generate frequencies above 350 MHz on multiple outputs simultaneously?

Yes, but with restriction: only two unique frequencies above 350 MHz may be generated simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints. For example, if Fvco = 2.84 GHz, outputs can be set to 710 MHz (Fvco/4) and 473.33 MHz (Fvco/6), but a third >350 MHz output must share one of those two values or fall below 350 MHz.

How is output voltage configured per channel on the SI5338A-B04361-GM?

Each output pair (CLK0A/B through CLK3A/B) has its own dedicated VDDO supply pin (VDDO0–VDDO3), allowing independent selection of 1.5 V, 1.8 V, 2.5 V, or 3.3 V per channel. This eliminates level-shifting components when driving mixed-voltage devices such as 1.8 V FPGAs and 3.3 V legacy peripherals from the same SI5338A-B04361-GM device.

Is ClockBuilder Pro software required to configure the SI5338A-B04361-GM?

No, ClockBuilder Pro is optional but strongly recommended. The SI5338A-B04361-GM can be programmed via standard I²C commands using any microcontroller or host processor. However, ClockBuilder Pro automates register configuration, validates timing constraints, generates initialization code, and performs jitter simulation - significantly reducing development time and risk of misconfiguration for the SI5338A-B04361-GM.

SI5338A-B04361-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B04361-GM FAQ

1.How can I place an order for SI5338A-B04361-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B04361-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B04361-GM reliable?

The price and inventory of SI5338A-B04361-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B04361-GM is usually 5 days.

3.What payment methods are accepted for SI5338A-B04361-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B04361-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B04361-GM?

SI5338A-B04361-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B04361-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B04361-GM?

For technical support, including SI5338A-B04361-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B04361-GM requirements.

6.How does Aetrix verify that SI5338A-B04361-GM is sourced from the original manufacturer or authorized distributors?

All SI5338A-B04361-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B04361-GM meets industry standards.

7.What is the process for return or replacement of SI5338A-B04361-GM?

All SI5338A-B04361-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B04361-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B04361-GM part is unused and in its original packaging.

Return procedure for SI5338A-B04361-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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