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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B04361-GMR

Name: SI5338A-B04361-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B04361-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B04361-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B04361-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338A-B04361-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338A-B04361-GMR datasheet, SI5338A-B04361-GMR pinout, SI5338A-B04361-GMR application, or SI5338A-B04361-GMR equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338A-B04361-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis blocks. Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats and can be configured for integer or fractional frequency synthesis.

It features loss-of-lock and loss-of-signal detection, independent phase adjustment (<20 ps step resolution), glitchless frequency increment/decrement (1 ppm steps), and external feedback mode for zero-delay operation. Input flexibility includes 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential references.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements at 125 MHz output
Output Frequency Range	0.16–710 MHz - supports PCIe 100 MHz HCSL, 156.25 MHz Ethernet, and 125 MHz USB 3.0 clocks
Input Reference Support	8–30 MHz crystal or 5–710 MHz differential - enables direct replacement of multiple XO sources
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.4–3.63 V - allows mixed-voltage system clock distribution
Package	24-pin QFN, 4 × 4 mm - fits dense FPGA/ASIC timing layouts with thermal resistance θJA = 37 °C/W
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
I²C Interface	Standard-mode (100 kHz) and fast-mode (400 kHz) - compatible with standard microcontroller GPIOs

Pinout & Package

SI5338A-B04361-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left (IN1), and pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept 5–710 MHz AC-coupled LVDS/LVPECL/CML; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support 5–200 MHz CMOS; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B–CLK3A/CLK3B	Differential clock outputs	Four independent pairs; each configurable as LVPECL/LVDS/HCSL/CML with selectable VDDOx
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output bank - enable mixed-signal voltage domain interfacing
SCL, SDA	I²C control interface	Standard SMBus-compatible bus; supports ClockBuilder Pro configuration and runtime updates
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm accuracy on all four outputs via independent fractional-N dividers
PCIe Gen 3 SRNS compliance	0.11–0.32 ps RMS jitter in Separate Reference No Spread mode - satisfies PCIe Base Spec 3.0
Independent phase adjustment	±45 ns range with <20 ps step resolution - supports precise skew alignment in multi-lane SerDes
Spread spectrum modulation	Configurable 0.5–5.0% down-spread at 33–63 kHz - reduces EMI in noise-sensitive systems
Glitchless frequency tuning	1 ppm step size with hardware pin control (PINC/FINC) - enables real-time clock rate adaptation without output disruption

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz HCSL clocks to PCIe Gen 4 switch ICs with strict jitter limits. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter reference clocks for upstream/downstream ports and management logic. Use Value: Meets PCIe Gen 4 Common Clock TJ < 33.6 ps pk-pk and RMS jitter < 0.45 ps - eliminates need for discrete oscillators per port.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 250 MHz clocks for 1/10 GbE PHYs and MACs in Layer 3 switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal. Use Value: Eliminates crystal inventory for multiple Ethernet standards; supports dynamic rate switching via I²C.
FPGA High-Speed Transceiver Clocking	Broadcast Video Timing
Use Scenario: Supplying clean, phase-aligned reference clocks to Xilinx Versal or Intel Agilex FPGA transceiver banks. IC Role / Device Role / Timing Role: Configurable clock source with independent VDDO per output - matches diverse I/O voltage domains (1.8 V LVDS, 1.2 V HCSL). Use Value: Achieves <10 ps pk-pk cycle-cycle jitter at 5+ GHz SerDes PMA rates - ensures robust link training and BER < 10⁻¹².	Use Scenario: Delivering SMPTE ST 2042/2082-compliant 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks to video processing ASICs. IC Role / Device Role / Timing Role: Low-phase-noise generator supporting both baseband and embedded sync signals across HD/4K/8K pipelines. Use Value: 0.7 ps RMS jitter preserves color fidelity and frame synchronization - avoids visible artifacts in broadcast-grade displays.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz HCSL clocks to PCIe Gen 4 switch ICs with strict jitter limits.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter reference clocks for upstream/downstream ports and management logic.

Use Value: Meets PCIe Gen 4 Common Clock TJ < 33.6 ps pk-pk and RMS jitter < 0.45 ps - eliminates need for discrete oscillators per port.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 250 MHz clocks for 1/10 GbE PHYs and MACs in Layer 3 switches.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal.

Use Value: Eliminates crystal inventory for multiple Ethernet standards; supports dynamic rate switching via I²C.

FPGA High-Speed Transceiver Clocking

Broadcast Video Timing

Use Scenario: Supplying clean, phase-aligned reference clocks to Xilinx Versal or Intel Agilex FPGA transceiver banks.

IC Role / Device Role / Timing Role: Configurable clock source with independent VDDO per output - matches diverse I/O voltage domains (1.8 V LVDS, 1.2 V HCSL).

Use Value: Achieves <10 ps pk-pk cycle-cycle jitter at 5+ GHz SerDes PMA rates - ensures robust link training and BER < 10⁻¹².

Use Scenario: Delivering SMPTE ST 2042/2082-compliant 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks to video processing ASICs.

IC Role / Device Role / Timing Role: Low-phase-noise generator supporting both baseband and embedded sync signals across HD/4K/8K pipelines.

Use Value: 0.7 ps RMS jitter preserves color fidelity and frame synchronization - avoids visible artifacts in broadcast-grade displays.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06181-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC timing and multi-core processor clock trees - not drop-in compatible	Choose when >4 outputs, sub-0.4 ps jitter, or deterministic latency are required; requires PCB redesign
ICS853S01AGI-01LFT	Fixed-frequency, non-programmable quad LVDS buffer; no synthesis, no I²C, 1.2 ps RMS jitter	Limited to static clock fanout; no frequency translation or spread spectrum	Select only for cost-sensitive, fixed-rate applications where programmability is unnecessary

Compared with Si5332A-D06181-GM and ICS853S01AGI-01LFT, SI5338A-B04361-GMR uniquely balances full I²C programmability, PCIe Gen 4 compliance, and 4-output flexibility in a compact 4 mm QFN - making it optimal for upgradeable timing architectures requiring field reconfiguration without layout changes.

Availability

SI5338A-B04361-GMR is available at Aetrix Electronics and suitable for PCIe switch timing, Ethernet switch clocking, FPGA transceiver reference, and broadcast video timing requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338A-B04361-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si5338 family is designed for high-performance, multi-protocol clock generation in datacenter, networking, and communications infrastructure - enabling consolidation of discrete oscillators into a single programmable timing IC.

FAQ

What is the maximum output frequency supported by SI5338A-B04361-GMR in LVPECL format?

The SI5338A-B04361-GMR supports up to 710 MHz in LVPECL output format, as specified in Table 6 of the datasheet. This capability enables direct clocking of high-speed SerDes lanes in PCIe Gen 4 and 100G Ethernet applications. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6) due to internal VCO constraints. The SI5338A-B04361-GMR must be configured using ClockBuilder Pro to ensure valid MultiSynth™ divider settings for target frequencies.

Does SI5338A-B04361-GMR support spread-spectrum clocking (SSC), and what are its configurable parameters?

Yes, SI5338A-B04361-GMR supports fully configurable spread-spectrum clocking on any output. It allows spread magnitude from 0.5% to 5.0% down-spread, modulation rates from 33 to 63 kHz, and operation across 5–350 MHz output frequencies. Default settings are ~0.5% down-spread at ~31.5 kHz. Configuration is performed via I²C registers or ClockBuilder Pro software. The SI5338A-B04361-GMR's SSC engine operates independently per output, enabling selective EMI reduction without affecting other clock domains.

Can SI5338A-B04361-GMR generate different output voltages on each of its four output banks?

Yes, SI5338A-B04361-GMR provides independent VDDOx supplies (VDDO0–VDDO3) that can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V per output bank. This allows simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) signaling from a single device - critical for interfacing with heterogeneous logic families in modern SoC/FPGA systems. Each VDDO rail powers its associated CLKxA/CLKxB pair, and voltage selection is configured via I²C register writes. The SI5338A-B04361-GMR's design eliminates level-shifter components in mixed-voltage timing trees.

How does SI5338A-B04361-GMR achieve PCIe Gen 3 Separate Reference No Spread (SRNS) compliance?

SI5338A-B04361-GMR achieves PCIe Gen 3 SRNS compliance through optimized PLL loop bandwidth (2–5 MHz), low intrinsic phase jitter (0.11–0.32 ps RMS), and deterministic jitter suppression. Its MultiSynth™ architecture ensures integer-mode synthesis with minimal fractional spurs, and the device passes Intel Clock Jitter Tool validation per AN562. The SI5338A-B04361-GMR must be configured with appropriate R-divider and N-divider values, and its reference input must meet slew rate requirements (>0.3 V/ns for differential inputs) to maintain compliance. External feedback mode further enhances stability in zero-delay configurations.

Is ClockBuilder Pro software required to configure SI5338A-B04361-GMR, or can it be programmed directly via I²C?

ClockBuilder Pro is not required but strongly recommended for initial configuration and validation of SI5338A-B04361-GMR. The device supports full I²C/SMBus programming (100/400 kHz) for runtime updates, register-level control, and field firmware upgrades. However, ClockBuilder Pro automates complex MultiSynth™ divider calculations, validates jitter performance, generates configuration files, and exports register maps - reducing risk of misconfiguration. All SI5338A-B04361-GMR devices ship pre-programmed with factory defaults, but custom timing profiles require either ClockBuilder Pro or verified register sequences. Direct I²C access remains fully supported for embedded host control.

SI5338A-B04361-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B04361-GMR FAQ

1.How can I place an order for SI5338A-B04361-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B04361-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B04361-GMR reliable?

The price and inventory of SI5338A-B04361-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B04361-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B04361-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B04361-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B04361-GMR?

SI5338A-B04361-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B04361-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B04361-GMR?

For technical support, including SI5338A-B04361-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B04361-GMR requirements.

6.How does Aetrix verify that SI5338A-B04361-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B04361-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B04361-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B04361-GMR?

All SI5338A-B04361-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B04361-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B04361-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B04361-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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