Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B04406-GM

Name: SI5338A-B04406-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B04406-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338A-B04406-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B04406-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,263

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338A-B04406-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338A-B04406-GM datasheet, SI5338A-B04406-GM pinout, SI5338A-B04406-GM application, or SI5338A-B04406-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% deviation), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338A-B04406-GM implements a two-stage PLL architecture: a high-stability reference stage (Phase Detector + Loop Filter + VCO) feeding four independent MultiSynth™ synthesis blocks, each with programmable R, M, N, P dividers and integer/fractional mode support. Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.

Each of the four output drivers supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage selection (1.5–3.3 V), programmable phase offset (±45 ns, <20 ps step), and glitchless frequency increment/decrement (1 ppm steps). External feedback enables zero-delay mode, while INTR pin provides loss-of-lock and loss-of-signal status reporting.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS).
Output Count & Type	Four independent outputs: supports up to four differential (LVPECL/LVDS/HCSL/CML) or eight single-ended (CMOS/SSTL/HSTL) clocks simultaneously.
Frequency Range	0.16–710 MHz per output; supports >350 MHz on two outputs simultaneously (Fvco/4 and Fvco/6).
Input Reference Options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3.
Operating Temp	–40 °C to +85 °C ambient; qualified for industrial and telecom line card environments.

Pinout & Package

SI5338A-B04406-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed across Si5338 family variants and validated per Skyworks Rev. 1.6 datasheet (page 37).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination.
IN3, IN4	Single-ended inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD.
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent output channels; each pair configurable as LVPECL/LVDS/HCSL/CML with dedicated VDDOx supply.
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enable mixed-voltage system interfacing.
VDD	Core supply	Single 1.8/2.5/3.3 V supply powers PLL, synthesizers, and logic; PSRR optimized for clean timing.
SCL, SDA	I²C interface	SMBus-compatible 2-wire serial bus (up to 400 kHz); used for configuration, status readback, and dynamic reprogramming.
INTR	Interrupt output	Open-drain active-low signal indicating loss-of-lock or loss-of-signal events; requires external pull-up.
OEB, PINC, FINC	Control inputs	Hardware pins for output enable, phase increment, and frequency increment; enable real-time glitchless adjustments without I²C traffic.

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers deliver true zero-ppm accuracy on all outputs with 1 ppb resolution.
PCIe Gen 4 compliance	Meets PCIe Base Spec 4.0 rev. 0.5 jitter requirements (0.15–0.45 ps RMS) in common clock mode with 2–5 MHz PLL bandwidth.
Independent output voltage	Each output bank (VDDO0–VDDO3) supports 1.5/1.8/2.5/3.3 V, enabling direct interface to mixed-voltage FPGAs, processors, and SerDes PHYs.
Spread-spectrum clocking	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate, reducing EMI in dense PCB layouts.
Glitchless frequency tuning	Hardware-controlled frequency increment/decrement (1 ppm steps) with 667 ns update time (>18 MHz outputs) avoids clock interruptions during dynamic scaling.
Loss-of-signal detection	Sub-5 µs detection (tLOS = 2.6–5 µs) and release (tLOSRLS = 0.01–1 µs) enable fast fault response in mission-critical timing systems.

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a 1U data center switch chassis. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter (<0.45 ps RMS) HCSL clocks meeting PCIe Gen 4 Common Clock jitter mask. Use Value: Eliminates need for four discrete oscillators; reduces board area by 65% and improves skew matching (<100 ps) between switch lanes.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and switch fabric interfaces in carrier-grade Ethernet routers. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3 compliant rates with independent format/voltage per port (LVDS for PHYs, CMOS for CPUs). Use Value: Enables single-device timing for multi-rate Ethernet platforms; eliminates external level translators and reduces BOM count by 7+ components.
Broadcast Video Timing	Processor & FPGA Clocking
Use Scenario: Delivering SMPTE ST 2082 (28.63636 MHz), ST 292 (27 MHz), and ST 424 (74.25 MHz) reference clocks to video encoder/decoder SoCs and serializer/deserializer ICs in 4K/8K broadcast equipment. IC Role / Device Role / Timing Role: Precision clock generator with <20 ps phase step resolution and ±45 ns programmable offset for frame-synchronized multi-channel video processing. Use Value: Achieves sub-pixel timing alignment across HD/SDI links; replaces crystal + divider chains with deterministic, software-tunable solution.	Use Scenario: Supplying 500 MHz processor core, 200 MHz DDR4 memory, 100 MHz peripheral, and 25 MHz debug clocks to heterogeneous SoC/FPGA-based industrial controllers. IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal domains: LVDS for DDR4, HCSL for CPU, CMOS for peripherals, all from one device. Use Value: Reduces power supply noise coupling via independent VDDO rails; simplifies layout with single 4×4 mm footprint instead of four discrete clock ICs.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a 1U data center switch chassis.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter (<0.45 ps RMS) HCSL clocks meeting PCIe Gen 4 Common Clock jitter mask.

Use Value: Eliminates need for four discrete oscillators; reduces board area by 65% and improves skew matching (<100 ps) between switch lanes.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and switch fabric interfaces in carrier-grade Ethernet routers.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3 compliant rates with independent format/voltage per port (LVDS for PHYs, CMOS for CPUs).

Use Value: Enables single-device timing for multi-rate Ethernet platforms; eliminates external level translators and reduces BOM count by 7+ components.

Broadcast Video Timing

Processor & FPGA Clocking

Use Scenario: Delivering SMPTE ST 2082 (28.63636 MHz), ST 292 (27 MHz), and ST 424 (74.25 MHz) reference clocks to video encoder/decoder SoCs and serializer/deserializer ICs in 4K/8K broadcast equipment.

IC Role / Device Role / Timing Role: Precision clock generator with <20 ps phase step resolution and ±45 ns programmable offset for frame-synchronized multi-channel video processing.

Use Value: Achieves sub-pixel timing alignment across HD/SDI links; replaces crystal + divider chains with deterministic, software-tunable solution.

Use Scenario: Supplying 500 MHz processor core, 200 MHz DDR4 memory, 100 MHz peripheral, and 25 MHz debug clocks to heterogeneous SoC/FPGA-based industrial controllers.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal domains: LVDS for DDR4, HCSL for CPU, CMOS for peripherals, all from one device.

Use Value: Reduces power supply noise coupling via independent VDDO rails; simplifies layout with single 4×4 mm footprint instead of four discrete clock ICs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B04405-GM	Same silicon; differs only in factory-programmed configuration (different default frequency set and I²C address).	Pre-configured for alternate reference input (e.g., 25 MHz vs. 100 MHz) and output frequency map; not field-reprogrammable to match SI5338A-B04406-GM defaults.	Select when requiring identical performance with preloaded settings aligned to specific platform reference clocks.
LMK04832ISQE/NOPB	Two PLLs (vs. one PLL + four MultiSynths), higher power (125 mA vs. 45 mA typ), larger 48-QFN package; supports JESD204B deterministic latency.	Targeted at RF/data converter timing with ultra-low additive jitter (<50 fs); less optimal for cost-sensitive PCIe/switch applications due to size and complexity.	Choose for JESD204B baseband systems where deterministic latency and sub-50 fs additive jitter outweigh size and power penalties.

Compared with Si5338A-B04405-GM, SI5338A-B04406-GM offers identical silicon performance but distinct factory configuration; compared with LMK04832ISQE/NOPB, SI5338A-B04406-GM delivers lower power, smaller footprint, and simpler programming for PCIe/switch/router use cases-without JESD204B features.

Availability

SI5338A-B04406-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338A-B04406-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed specifically for high-performance, multi-output clock generation in space-constrained, jitter-sensitive applications such as PCIe Gen 4, 10G/25G Ethernet, and broadcast video infrastructure.

FAQ

What is the maximum output frequency supported by SI5338A-B04406-GM?

The SI5338A-B04406-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6), as confirmed in Table 6 of the Skyworks Rev. 1.6 datasheet.

Does SI5338A-B04406-GM support PCIe Gen 4 Common Clock compliance?

Yes, SI5338A-B04406-GM meets PCIe Gen 4 Common Clock jitter specifications (0.15–0.45 ps RMS) when configured with a 2–5 MHz PLL bandwidth and 100 MHz HCSL outputs, as verified in Table 12 of the Skyworks Rev. 1.6 datasheet and validated using the Skyworks PCIe Clock Jitter Tool.

How many independent output voltage supplies does SI5338A-B04406-GM provide?

SI5338A-B04406-GM provides four independent output buffer supply pins-VDDO0, VDDO1, VDDO2, and VDDO3-each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V to match diverse load requirements without external level shifters.

Can SI5338A-B04406-GM generate spread-spectrum clocking on individual outputs?

Yes, SI5338A-B04406-GM supports independent spread-spectrum clocking on any output with user-selectable parameters: deviation (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread only). Default is 0.5% down-spread at ~31.5 kHz, per Table 5 notes.

What is the function of the INTR pin on SI5338A-B04406-GM?

The INTR pin on SI5338A-B04406-GM is an open-drain interrupt output that asserts low to indicate loss-of-lock (LOL) or loss-of-signal (LOS) conditions. Its detection times are tLOL = 5–10 ms and tLOS = 2.6–5 µs, enabling rapid system-level fault response without polling the I²C interface.

SI5338A-B04406-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Obsolete

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B04406-GM FAQ

1.How can I place an order for SI5338A-B04406-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B04406-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B04406-GM reliable?

The price and inventory of SI5338A-B04406-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B04406-GM is usually 5 days.

3.What payment methods are accepted for SI5338A-B04406-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B04406-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B04406-GM?

SI5338A-B04406-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B04406-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B04406-GM?

For technical support, including SI5338A-B04406-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B04406-GM requirements.

6.How does Aetrix verify that SI5338A-B04406-GM is sourced from the original manufacturer or authorized distributors?

All SI5338A-B04406-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B04406-GM meets industry standards.

7.What is the process for return or replacement of SI5338A-B04406-GM?

All SI5338A-B04406-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B04406-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B04406-GM part is unused and in its original packaging.

Return procedure for SI5338A-B04406-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…