Skyworks Solutions Inc. SI5338A-B04407-GMR
- Part No.:
- SI5338A-B04407-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338A-B04407-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:4,189
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338A-B04407-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338A-B04407-GMR datasheet, SI5338A-B04407-GMR pinout, SI5338A-B04407-GMR application, or SI5338A-B04407-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ frequency synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation), and loss-of-lock/loss-of-signal alarm support.
Technical Context
The SI5338A-B04407-GMR implements a two-stage PLL architecture: a high-stability reference stage (Phase Detector + Loop Filter + VCO) feeding four independent MultiSynth™ fractional-N synthesis blocks, each driving a configurable output buffer. Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.
Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage (1.5–3.3 V), phase adjustment (<20 ps steps), frequency increment/decrement (1 ppm steps), and spread-spectrum generation. The device operates across –40 to +85 °C and integrates OTP NVM for factory programming.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS) |
| Output Count & Type | 4 independent outputs; supports up to 4 differential or 8 single-ended clocks, or mixed configuration |
| Frequency Range | 0.16–710 MHz per output; LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz |
| Input Reference Options | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating Temperature | –40 °C to +85 °C ambient; qualified for industrial and telecom line card environments |
Pinout & Package
SI5338A-B04407-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification and validated for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential input pair 1 | Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination |
| IN3, IN4 | Single-ended input pair | Supports 5–200 MHz CMOS inputs; VIH = 0.7×VDD, VIL = 0.3×VDD |
| IN5, IN6 | Differential input pair 2 | Second 5–710 MHz differential input; identical electrical specs to IN1/IN2 |
| CLK0A, CLK0B | Differential output 0 | LVPECL/LVDS/HCSL/CML configurable; VDDO0 supplies output buffer |
| CLK1A, CLK1B | Differential output 1 | Independent format/voltage/frequency; VDDO1 supplies buffer |
| CLK2A, CLK2B | Differential output 2 | Configurable per MultiSynth™ block M2; VDDO2 supplies buffer |
| CLK3A, CLK3B | Differential output 3 | Configurable per MultiSynth™ block M3; VDDO3 supplies buffer |
| VDD, VDDO0–VDDO3 | Power supplies | VDD = core supply (1.8/2.5/3.3 V); VDDOx = independent output buffer supplies (1.5–3.3 V) |
| SCL, SDA | I²C interface | SMBus-compatible serial interface (up to 400 kHz); supports ClockBuilder Pro programming |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) |
| RSVD_GND | Reserved ground | Internal test pin; must be connected to GND per layout guidelines |
| GND | Ground | Eight dedicated GND pins; required for low-noise clock distribution and thermal dissipation |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ any-frequency synthesis | Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs simultaneously |
| PCIe Gen 4 Common Clock compliance | 0.15–0.45 ps RMS jitter at 100 MHz HCSL output; validated per PCIe Base Spec 4.0 rev. 0.5 |
| Independent output voltage per driver | Each of four output banks supports 1.5 V, 1.8 V, 2.5 V, or 3.3 V-enabling mixed-voltage system clocking |
| Glitchless frequency tuning | 1 ppm step size with <667 ns update time via PIN or I²C; no output interruption during adjustment |
| Programmable spread spectrum | Configurable 0.5–5.0% down-spread at 33–63 kHz on any output-reducing EMI without affecting timing integrity |
| Loss-of-lock and loss-of-signal alarms | Active-low INTR pin asserts within 10 ms LOL and 5 µs LOS-enabling real-time system fault detection |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: High-density 1U switch chassis requiring synchronized 100 MHz reference clocks for multiple PCIe Gen 4 x16 slots and 10 GbE PHYs. IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter PCIe-compliant clocks with spread-spectrum control per port group. Use Value: Eliminates four discrete oscillators; reduces board area by >60% while meeting PCIe Gen 4 TJ < 3.0 ps pk-pk and SRNS jitter requirements. |
Use Scenario: Carrier-grade Ethernet aggregation switch supporting 1 GbE and 10 GbE interfaces with strict IEEE 802.3 jitter limits. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating 125 MHz (1 GbE), 156.25 MHz (10 GbE), and 625 MHz (internal SerDes) from a single 25 MHz crystal. Use Value: Achieves 0.38 ps RMS random jitter (GbE band) and 0.7 ps RMS OC-12 jitter-ensuring BER < 10⁻¹² across all ports. |
| Broadcast Video Timing | FPGA/Processor Clocking |
Use Scenario: SMPTE ST 2082-1 compliant 12G-SDI video router requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with sub-20 ps skew. IC Role / Device Role / Timing Role: Multi-format clock generator delivering LVDS and HCSL outputs with programmable phase offset (<20 ps steps) for skew alignment. Use Value: Enables deterministic inter-output skew ≤100 ps and phase adjustment resolution matching SDI eye diagram timing margins. |
Use Scenario: Heterogeneous compute platform integrating Xilinx Versal FPGA, ARM-based SoC, and DDR4 memory subsystem-each requiring distinct clock frequencies and voltage levels. IC Role / Device Role / Timing Role: Configurable clock source supplying 100 MHz (FPGA logic), 500 MHz (ARM AXI), and 1.2 GHz (DDR4 PHY) from one device. Use Value: Independent VDDOx supplies allow simultaneous 1.8 V (FPGA I/O), 1.0 V (ARM core), and 1.2 V (DDR4) clock buffering-reducing BOM count by 3 ICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06409-GM | Higher integration: 8 outputs, integrated jitter cleaner, lower 0.35 ps RMS jitter; requires external 100 MHz reference for optimal performance | Targeted at ultra-low-jitter 5G wireless infrastructure and optical transport where sub-0.4 ps RMS is mandatory | Select when PCIe Gen 5 or OTN OC-192 timing is required; not drop-in due to different pinout and register map |
| ICS8430I-01T | Fixed-function 4-output LVDS generator; no I²C programmability; 1.2 ps RMS jitter; only supports 10–350 MHz outputs | Cost-sensitive industrial control systems using fixed 100/125/156.25 MHz clocks without spread spectrum or voltage flexibility | Choose for simple, unprogrammable clock fanout where design lock-in is acceptable and BOM cost is primary constraint |
Compared with Si5332A-D06409-GM, SI5338A-B04407-GMR offers broader input flexibility (crystal direct drive, wider frequency range) and lower system-level design complexity; versus ICS8430I-01T, it delivers field-programmable frequency agility and multi-voltage support essential for evolving high-speed serial standards.
Availability
SI5338A-B04407-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338A-B04407-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.
The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-where flexible frequency synthesis and signal integrity are critical.
FAQ
What is the maximum output frequency supported by SI5338A-B04407-GMR in LVPECL mode?
The SI5338A-B04407-GMR supports LVPECL outputs up to 710 MHz, as specified in Table 6 of the Skyworks datasheet. This capability enables direct clocking of high-speed SerDes lanes in PCIe Gen 4 and 10 GbE applications without external frequency multiplication. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6) per the MultiSynth™ architecture.
Does SI5338A-B04407-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?
Yes, SI5338A-B04407-GMR is explicitly validated for PCIe Gen 3 SRNS and Gen 4 Common Clock modes. Its 0.11–0.32 ps RMS jitter in Gen 3 SRNS (PLL BW 2–5 MHz, CDR = 10 MHz) and 0.15–0.45 ps RMS in Gen 4 Common Clock meet PCI-SIG specifications per Table 12 of the datasheet.
Can SI5338A-B04407-GMR generate four different output frequencies simultaneously?
Yes, SI5338A-B04407-GMR uses four independent MultiSynth™ fractional-N synthesizers to generate four fully independent output frequencies-each configurable from 0.16 MHz to 710 MHz depending on format. All outputs achieve true zero-ppm precision without shared dividers or frequency constraints.
What is the purpose of the RSVD_GND pin on SI5338A-B04407-GMR?
The RSVD_GND pin on SI5338A-B04407-GMR is an internal test node reserved for factory characterization. Skyworks documentation mandates connection to system ground (GND) in all PCB layouts to ensure proper thermal dissipation, noise immunity, and functional reliability-failure to tie it to GND may impact jitter performance or device stability.
How does the I²C interface of SI5338A-B04407-GMR support field reprogramming?
The SI5338A-B04407-GMR features a standard SMBus-compatible I²C interface (SCL/SDA) supporting read/write access to all configuration registers and OTP NVM. Using Skyworks' ClockBuilder Pro software, engineers can generate custom configurations, validate timing margins, and program the device in-system-enabling late-stage frequency changes without hardware modification.
SI5338A-B04407-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338A-B04407-GMR FAQ
1.How can I place an order for SI5338A-B04407-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338A-B04407-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338A-B04407-GMR reliable?
The price and inventory of SI5338A-B04407-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B04407-GMR is usually 5 days.
3.What payment methods are accepted for SI5338A-B04407-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B04407-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338A-B04407-GMR?
SI5338A-B04407-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338A-B04407-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338A-B04407-GMR?
For technical support, including SI5338A-B04407-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B04407-GMR requirements.
6.How does Aetrix verify that SI5338A-B04407-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338A-B04407-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B04407-GMR meets industry standards.
7.What is the process for return or replacement of SI5338A-B04407-GMR?
All SI5338A-B04407-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B04407-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338A-B04407-GMR part is unused and in its original packaging.
Return procedure for SI5338A-B04407-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338A-B04407-GMR Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

