Skyworks Solutions Inc. SI5338A-B04519-GM
- Part No.:
- SI5338A-B04519-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338A-B04519-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:2,168
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338A-B04519-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent differential or single-ended clocks (0.16–710 MHz), 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338A-B04519-GM datasheet, SI5338A-B04519-GM pinout, SI5338A-B04519-GM application, or SI5338A-B04519-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), programmable phase/frequency adjustment (<20 ps / 1 ppm steps), spread-spectrum capability (0.5–5.0% at 33–63 kHz), and support for multiple input references (crystal, CMOS, SSTL/HSTL, differential).
Technical Context
The SI5338A-B04519-GM implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to an external crystal or clock input (5–710 MHz), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating outputs with true zero-ppm accuracy. Each output path includes configurable divider chains (R/M/N/P), independent voltage rails (VDDO0–VDDO3), and selectable signal formats (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL).
It supports both free-running synthesis and synchronous frequency translation modes, with external feedback enabling zero-delay operation. Real-time control is enabled via I²C/SMBus interface, with dedicated pins (PINC/FINC, OEB) for glitchless frequency/phase increment/decrement and output enable/disable without software intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS) |
| Output Frequency Range | 0.16–710 MHz per channel; supports ≥2 outputs >350 MHz simultaneously (Fvco/4 & Fvco/6) |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Output Format Flexibility | LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL per channel; independent VDDO (1.5/1.8/2.5/3.3 V) |
| Programmable Features | Independent phase offset (±45 ns, <20 ps step), frequency step (1 ppm), spread spectrum (0.5–5.0%, 33–63 kHz) |
| Supply & Environment | Core: 1.8/2.5/3.3 V ±10%; operating temp: –40 to +85 °C; 45 mA typical core current @ 100 MHz all outputs |
Pinout & Package
SI5338A-B04519-GM is housed in a 4 × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments are standardized across Si5338 variants per Skyworks documentation (Rev. 1.6, p.33–36). The device uses a dual-input reference architecture (IN1/IN2 differential, IN3/IN4 single-ended, IN5/IN6 differential) and provides four differential clock pairs (CLK0A/B through CLK3A/B), six VDDO supplies (VDDO0–VDDO3), dual core VDD, I²C interface (SCL/SDA), interrupt (INTR), and reserved ground (RSVD_GND).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1/IN2, IN5/IN6 | Differential clock inputs | Accept 5–710 MHz AC-coupled LVDS/CML; require external 100 Ω termination |
| IN3/IN4 | Single-ended clock inputs | Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; DC-coupled with internal bias |
| CLK0A/B–CLK3A/B | Differential clock outputs | Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CML with dedicated VDDO |
| VDDO0–VDDO3 | Output buffer supply rails | Enable per-output voltage selection (1.5/1.8/2.5/3.3 V) to match downstream logic |
| SCL/SDA | I²C/SMBus interface | Standard 2-wire serial programming; supports ClockBuilder Pro configuration |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock (LOL) or loss-of-signal (LOS) |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers deliver any-frequency outputs (0.16–710 MHz) with 0 ppm precision |
| PCIe Gen 4 compliance | Meets Common Clock jitter spec (0.15–0.45 ps RMS) and SRNS requirements for Gen 3; validated with Intel Clock Jitter Tool |
| Glitchless frequency tuning | Hardware-controlled PINC/FINC pins enable real-time 1 ppm frequency increments without software or PLL relock |
| Per-output voltage & format | Each of four outputs supports independent VDDO (1.5/1.8/2.5/3.3 V) and signal format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) |
| Spread-spectrum clocking | Configurable SSC on any output: 5–350 MHz range, 0.5–5.0% spread, 33–63 kHz modulation rate for EMI reduction |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter (≤0.45 ps RMS) HCSL clocks meeting PCIe Gen 4 Common Clock specification. Use Value: Eliminates need for four discrete oscillators; enables deterministic skew control between lanes and supports spread-spectrum for EMI compliance. |
Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and SerDes in a modular Ethernet switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing precise Ethernet-compliant frequencies from a single 25 MHz crystal reference. Use Value: Reduces BOM count and board space vs. multiple fixed-frequency oscillators; supports dynamic reconfiguration for multi-rate PHY support. |
| Broadcast Video Timing | FPGA/Processor Clocking |
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) and ST 2081 (12 Gbps) reference clocks to video encoder/decoder ASICs in broadcast infrastructure. IC Role / Device Role / Timing Role: High-frequency differential clock generator supporting 270 MHz, 540 MHz, and 710 MHz outputs in LVPECL/LVDS formats. Use Value: Achieves sub-1 ps RMS jitter required for 27 Gbps serial links; independent phase adjustment aligns sampling edges across multiple video pipelines. |
Use Scenario: Supplying core, memory, and peripheral clocks (e.g., 1 GHz CPU, 800 MHz DDR4, 100 MHz PCIe) to heterogeneous SoCs and FPGAs in industrial control systems. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage rails matching diverse I/O standards (HSTL, SSTL, LVDS). Use Value: Simplifies power domain management; eliminates level-shifting components by driving each interface at its native voltage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B04520-GM | Same silicon; factory-programmed with different default configuration (B04520 vs. B04519) - distinct NVM OTP settings | Targeted for alternate reference frequency or output format defaults; not interchangeable without reprogramming | Select B04519 for preconfigured PCIe Gen 4 timing; verify ClockBuilder Pro configuration compatibility before substitution |
| LMK04832ISQE/NOPB | Two PLLs (not four independent synthesizers); higher power (120 mA typ); larger 7 × 7 mm 48-VQFN package | Optimized for ultra-low jitter (<0.1 ps RMS) in RF/data converter apps; less flexible for multi-format, multi-voltage routing | Choose LMK04832 only when sub-0.2 ps RMS jitter is mandatory and board area/power budget permits |
Compared with SI5338A-B04519-GM, Si5338A-B04520-GM offers identical hardware but different factory OTP settings, requiring reprogramming for functional equivalence; LMK04832ISQE/NOPB delivers lower jitter but lacks per-output voltage/format flexibility and occupies 2.25× more PCB area.
Availability
SI5338A-B04519-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and broadcast video timing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5338A-B04519-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for communications infrastructure, automotive, and industrial markets.
The Si5338 family is designed as a highly configurable, low-jitter clock generator platform for replacing multiple fixed-frequency oscillators in high-speed serial interface systems including PCIe, Ethernet, Fibre Channel, and broadcast video.
FAQ
What is the primary function of the SI5338A-B04519-GM in a system design?
The SI5338A-B04519-GM serves as a quad-output, I²C-programmable clock generator that synthesizes four independent, low-jitter clock signals from a single reference input. Its core function is to replace up to four discrete crystal oscillators while enabling precise frequency, phase, voltage, and format control per output-critical for synchronizing high-speed serial interfaces like PCIe Gen 4 and 10 GbE. SI5338A-B04519-GM achieves this using Skyworks' patented MultiSynth™ technology.
Does the SI5338A-B04519-GM support PCIe Gen 4 timing requirements?
Yes, the SI5338A-B04519-GM is explicitly compliant with PCIe Gen 4 Common Clock jitter specifications, delivering ≤0.45 ps RMS jitter (12 kHz–20 MHz) when configured per Skyworks' validated test conditions (e.g., 100 MHz HCSL outputs). It also meets PCIe Gen 3 SRNS requirements and is verified using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4. SI5338A-B04519-GM supports both common clock and separate reference architectures.
How many independent output voltages can be configured on the SI5338A-B04519-GM?
The SI5338A-B04519-GM supports four independent output supply rails-VDDO0, VDDO1, VDDO2, and VDDO3-each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows each of its four output drivers to drive different logic families (e.g., LVDS at 2.5 V, HCSL at 1.8 V, CMOS at 3.3 V) simultaneously without external level shifters. SI5338A-B04519-GM's per-output voltage control is implemented via dedicated register settings and hardware pin strapping options.
Can the SI5338A-B04519-GM generate frequencies above 350 MHz on all four outputs simultaneously?
No. While the SI5338A-B04519-GM supports output frequencies up to 710 MHz, only two unique frequencies above 350 MHz can be generated simultaneously-specifically Fvco/4 and Fvco/6-due to internal VCO and divider architecture constraints. Outputs above 350 MHz must share these two synthesized frequencies. Lower-frequency outputs (≤350 MHz) retain full independence. SI5338A-B04519-GM's datasheet (Rev. 1.6, p.8, Table 6 note 6) explicitly defines this limitation.
What programming interface does the SI5338A-B04519-GM use, and is external configuration required?
The SI5338A-B04519-GM uses an I²C/SMBus-compatible 2-wire serial interface for full register-level configuration. Programming is performed via SCL/SDA pins, and Skyworks' ClockBuilder Pro software provides GUI-based setup, validation, and OTP programming. SI5338A-B04519-GM ships with factory-programmed OTP NVM (B04519 configuration), so it operates immediately upon power-up-but field reconfiguration is fully supported without requiring external nonvolatile memory.
SI5338A-B04519-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338A-B04519-GM FAQ
1.How can I place an order for SI5338A-B04519-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338A-B04519-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338A-B04519-GM reliable?
The price and inventory of SI5338A-B04519-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B04519-GM is usually 5 days.
3.What payment methods are accepted for SI5338A-B04519-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B04519-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338A-B04519-GM?
SI5338A-B04519-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338A-B04519-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338A-B04519-GM?
For technical support, including SI5338A-B04519-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B04519-GM requirements.
6.How does Aetrix verify that SI5338A-B04519-GM is sourced from the original manufacturer or authorized distributors?
All SI5338A-B04519-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B04519-GM meets industry standards.
7.What is the process for return or replacement of SI5338A-B04519-GM?
All SI5338A-B04519-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B04519-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338A-B04519-GM part is unused and in its original packaging.
Return procedure for SI5338A-B04519-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338A-B04519-GM Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

