Skyworks Solutions Inc. SI5338A-B04974-GM
- Part No.:
- SI5338A-B04974-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338A-B04974-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338A-B04974-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338A-B04974-GM datasheet, SI5338A-B04974-GM pinout, SI5338A-B04974-GM application, or SI5338A-B04974-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ frequency synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro support.
Technical Context
The SI5338A-B04974-GM implements a two-stage PLL architecture: a high-stability reference stage (Phase Frequency Detector + Loop Filter + VCO) feeding four independent MultiSynth™ fractional-N synthesis blocks, each driving a configurable output buffer. It supports external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) inputs.
Each of the four output drivers supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage selection (1.5–3.3 V), programmable phase offset (±45 ns, <20 ps step), and glitchless frequency increment/decrement (1 ppm steps). The device includes loss-of-lock and loss-of-signal alarms, external feedback for zero-delay mode, and I²C-based OTP NVM configuration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS) |
| Output Count & Flexibility | 4 independent outputs: up to 4 differential, 8 single-ended, or mixed; each configurable for format and voltage |
| Frequency Range | LVPECL/LVDS: 0.16–710 MHz; HCSL: 0.16–250 MHz; CMOS: 0.16–200 MHz; SSTL/HSTL: 0.16–350 MHz |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating Temperature | –40 °C to +85 °C ambient; qualified for industrial and telecom line card environments |
Pinout & Package
The SI5338A-B04974-GM is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks' Si5338 family layout and validated for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential input pair #1 | Accepts AC-coupled differential reference (5–710 MHz); internal 100 Ω termination enabled |
| IN3, IN4 | Single-ended input pair | Supports CMOS/SSTL/HSTL (5–350 MHz); 20 kΩ pull-up/pull-down configurable via register |
| CLK0A, CLK0B – CLK3A, CLK3B | Differential output pairs | Four independent LVPECL/LVDS/HCSL/CML outputs; each with dedicated VDDOx supply pin |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5/1.8/2.5/3.3 V rails per output driver; enables mixed-voltage system interfacing |
| SCL, SDA | I²C/SMBus interface | Standard 100/400 kHz operation; supports ClockBuilder Pro programming and runtime reconfiguration |
| INTR | Interrupt output | Open-drain status flag for loss-of-lock, loss-of-signal, or PLL unlock events |
| VDD | Core supply | Single 1.8/2.5/3.3 V rail powers PLL, synthesizers, and logic; PSRR optimized for noisy environments |
| GND / RSVD_GND | Ground terminals | Multiple GND pins and reserved ground pad ensure low-impedance return path and thermal dissipation |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs simultaneously |
| PCIe Gen 4 compliance | Validated 0.15–0.45 ps RMS jitter in Common Clock mode; supports SRNS for Gen 3 and CDR lock for Gen 4 |
| Glitchless frequency tuning | Pin- or I²C-controlled frequency increment/decrement in 1 ppm steps without output interruption |
| Programmable phase alignment | ±45 ns phase offset per output with <20 ps resolution; enables precise skew management across multi-lane interfaces |
| Spread-spectrum clocking | Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI |
| Flexible input handling | Five input options (IN1–IN6) supporting crystal, single-ended, and differential references with automatic detection |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched phase alignment. Use Value: Enables deterministic lane-to-lane skew control (<100 ps) and meets PCIe Gen 4 total jitter limit (≤33.6 ps pk-pk) without external jitter cleaners. |
Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and packet processors in a modular router line card. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer replacing discrete oscillators and translating between Ethernet line rates. Use Value: Reduces BOM count by 4× vs. discrete XO solution while maintaining <0.7 ps RMS jitter required for 25G KR compliance. |
| Broadcast Video Timing | FPGA/Processor Clocking |
Use Scenario: Delivering SMPTE ST 2082 (28.63636 MHz) and ST 2081 (74.25 MHz) reference clocks to video encoder/decoder FPGAs in a 4K/8K broadcast encoder. IC Role / Device Role / Timing Role: Precision frequency translator generating exact broadcast-standard frequencies from a single 25 MHz crystal. Use Value: Achieves true zero-ppm accuracy across all outputs using MultiSynth™ integer-mode synthesis, eliminating frame sync drift. |
Use Scenario: Supplying core, DDR, and peripheral clocks (e.g., 100 MHz, 200 MHz, 300 MHz) to Xilinx Versal and Intel Agilex FPGAs in AI inference accelerators. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage per output to match FPGA bank requirements. Use Value: Supports mixed-voltage FPGA designs (1.0 V core, 1.2 V DDR, 1.8 V peripherals) with single-device power domain isolation and <10 ps inter-output skew. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B05081-GM | Same Si5338A die; factory-programmed for PCIe Gen 4 SRNS + 100/125/156.25/312.5 MHz outputs | Fixed-frequency variant; no field reprogramming required for standard Ethernet/PCIe use cases | Select when pre-configured outputs eliminate need for I²C initialization in production boot flow |
| LMK04832RHAR | Two PLLs (jitter cleaner + synthesizer); higher integration (integrated LDOs, SPI interface); 0.18 ps RMS jitter | Requires external 100 MHz reference; better suited for ultra-low-jitter RF/data converter clocking than PCIe switching | Select when sub-0.2 ps RMS jitter and dual-loop cleaning are mandatory, and SPI is preferred over I²C |
Compared with SI5338A-B04974-GM, Si5338A-B05081-GM trades field programmability for faster time-to-operate in fixed-frequency systems, while LMK04832RHAR offers superior jitter performance at the cost of higher power (125 mA vs. 45 mA) and no crystal oscillator support.
Availability
SI5338A-B04974-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet routing infrastructure, broadcast video synchronization, and FPGA-based AI accelerator clocking requiring stable component supply across extended product lifecycles.
Supply support for SI5338A-B04974-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.
The Si5338 family was designed as a programmable, low-jitter clock generator platform targeting high-speed serial interface timing in networking, computing, and broadcast equipment-emphasizing flexibility, PCIe compliance, and space-constrained board layouts.
FAQ
What is the primary function of the SI5338A-B04974-GM in a PCIe Gen 4 system?
The SI5338A-B04974-GM serves as a quad-output clock generator delivering four independent, low-jitter reference clocks compliant with PCIe Gen 4 Common Clock specifications (≤0.45 ps RMS jitter). It replaces multiple discrete oscillators while enabling precise phase alignment across lanes-critical for maintaining signal integrity in high-speed switch and endpoint designs. SI5338A-B04974-GM achieves this using its patented MultiSynth™ architecture and validated PLL loop bandwidth settings.
Does the SI5338A-B04974-GM support crystal oscillator input, and what frequency range is supported?
Yes, the SI5338A-B04974-GM supports external crystal input on dedicated pins with a frequency range of 8 to 30 MHz. It includes on-chip load capacitance options (11–13 pF supported, 17–19 pF recommended) and accommodates crystals with ESR ≤300 Ω and drive level ≤100 µW. This capability allows SI5338A-B04974-GM to operate as a self-contained timing solution without requiring external clock sources.
Can the SI5338A-B04974-GM generate different output voltages on each channel, and which levels are supported?
Yes, the SI5338A-B04974-GM provides independent output buffer supply pins (VDDO0–VDDO3) enabling distinct voltage levels per output driver. Supported levels are 1.5 V, 1.8 V, 2.5 V, and 3.3 V-allowing direct interface with mixed-voltage devices such as FPGAs with separate I/O banks. This feature is implemented in hardware and configured via I²C registers, making SI5338A-B04974-GM suitable for complex heterogeneous system timing.
How is the SI5338A-B04974-GM programmed, and is external hardware required?
The SI5338A-B04974-GM is programmed via an I²C/SMBus-compatible serial interface using standard 100/400 kHz protocols. No external hardware programmer is required-configuration is performed using Skyworks' ClockBuilder Pro software running on a PC connected via USB-to-I²C adapter. SI5338A-B04974-GM stores settings in one-time-programmable (OTP) memory, enabling autonomous operation after initial setup.
What thermal and power characteristics define the SI5338A-B04974-GM's suitability for dense PCB layouts?
The SI5338A-B04974-GM operates with 45 mA typical core supply current at 100 MHz output and features a 4 × 4 mm QFN package with exposed thermal pad. Its junction-to-ambient thermal resistance (θJA) is 37 °C/W under still-air conditions, and it supports industrial temperature range (–40 °C to +85 °C). These characteristics allow SI5338A-B04974-GM to maintain stable timing performance in thermally constrained networking and telecom modules without forced airflow.
SI5338A-B04974-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338A-B04974-GM FAQ
1.How can I place an order for SI5338A-B04974-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338A-B04974-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338A-B04974-GM reliable?
The price and inventory of SI5338A-B04974-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B04974-GM is usually 5 days.
3.What payment methods are accepted for SI5338A-B04974-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B04974-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338A-B04974-GM?
SI5338A-B04974-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338A-B04974-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338A-B04974-GM?
For technical support, including SI5338A-B04974-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B04974-GM requirements.
6.How does Aetrix verify that SI5338A-B04974-GM is sourced from the original manufacturer or authorized distributors?
All SI5338A-B04974-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B04974-GM meets industry standards.
7.What is the process for return or replacement of SI5338A-B04974-GM?
All SI5338A-B04974-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B04974-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338A-B04974-GM part is unused and in its original packaging.
Return procedure for SI5338A-B04974-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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