Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B05001-GM

Name: SI5338A-B05001-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B05001-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338A-B05001-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B05001-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,542

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338A-B05001-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, processor/FPGA clocking, and PCIe timing systems.

For engineers reviewing the SI5338A-B05001-GM datasheet, SI5338A-B05001-GM pinout, SI5338A-B05001-GM application, or SI5338A-B05001-GM equivalent, key selection criteria include its MultiSynth™ any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with high-density PCB layouts.

Technical Context

The SI5338A-B05001-GM implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving a configurable output buffer. Its core operates from a single 1.8/2.5/3.3 V supply with 45 mA typical current draw.

Each of the four output drivers supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage rails (VDDO0–VDDO3), programmable phase offset (<20 ps steps), and glitchless frequency increment/decrement in 1 ppm steps. Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical - meets PCIe Gen 3/4 SRNS and GbE jitter requirements
Output Frequency Range	0.16–710 MHz - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, and Fibre Channel 1.0625 GHz (via /2 divider)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), differential (5–710 MHz) - enables flexible system clock sourcing
Output Format Flexibility	LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL - allows direct interface to FPGAs, processors, and SerDes without level-shifting
Supply Voltage	Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V - supports mixed-voltage system designs
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm - compact footprint compatible with automated SMT assembly

Pinout & Package

SI5338A-B05001-GM uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Rev. 1.6 datasheet and optimized for low-inductance clock routing and thermal dissipation.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended input pins	Support 5–200 MHz CMOS inputs; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B–CLK3A/CLK3B	Differential output pairs	Four independent output channels; each configurable as LVPECL/LVDS/HCSL/CML
VDDO0–VDDO3	Output buffer supply rails	Independent 1.4–3.63 V supplies per output bank enable mixed-signal interfacing
SCL/SDA	I²C serial interface	SMBus-compatible 100/400 kHz control bus; supports in-system programming and dynamic reconfiguration
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs simultaneously
PCIe Gen 4 compliance	0.15–0.45 ps RMS jitter in Common Clock mode meets PCIe Base Spec 4.0 rev. 0.5 requirements
Spread spectrum	Configurable down-spread (0.5–5.0%) at 33–63 kHz modulation rate to reduce EMI in dense PCBs
Glitchless frequency tuning	Pin-controlled or I²C-based frequency increment/decrement in 1 ppm steps without output interruption
Programmable phase offset	±45 ns range with <20 ps resolution per output - enables precise skew management in multi-lane interfaces
External feedback mode	Supports zero-delay configuration for clock distribution networks requiring matched input-to-output latency

Applications

Ethernet Switch/Router Timing	PCIe Gen 1–4 Clocking
Use Scenario: High-port-count 1/10 GbE switches requiring synchronous 125 MHz and 156.25 MHz clocks with sub-1 ps jitter. IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter Ethernet reference clocks with independent voltage and format control. Use Value: Eliminates four discrete oscillators; reduces board area by >60% while meeting IEEE 802.3 jitter masks via 0.7 ps RMS performance.	Use Scenario: Server motherboard with multiple PCIe slots requiring Gen 3/4 Common Clock and SRNS-compliant timing. IC Role / Device Role / Timing Role: Primary clock source delivering 100 MHz differential HCSL clocks with PCIe Gen 4 Common Clock jitter compliance. Use Value: Meets 0.15–0.45 ps RMS jitter requirement across all lanes; supports simultaneous Gen 3 SRNS and Gen 4 CC modes via register configuration.
Processor & FPGA Clocking	Broadcast Video/Audio Timing
Use Scenario: Heterogeneous SoC platform with ARM CPU, GPU, DDR4 memory, and FPGA fabric needing distinct clock domains. IC Role / Device Role / Timing Role: Centralized clock synthesizer generating 500 MHz (CPU), 300 MHz (GPU), 1333 MHz (DDR4), and 100 MHz (FPGA logic) from one reference. Use Value: Independent MultiSynth™ blocks enable integer/fractional synthesis per domain; eliminates inter-clock crosstalk via isolated output buffers.	Use Scenario: SMPTE ST 2082/2081 video router requiring SMPTE 2082 (270 MHz), ST 2081 (12 Gbps), and AES3 audio (48 kHz) clocks. IC Role / Device Role / Timing Role: Broadcast-grade timing IC delivering ultra-low-jitter 270 MHz LVPECL and 48 kHz CMOS clocks from a single 27 MHz crystal. Use Value: 0.7 ps RMS jitter ensures compliance with SMPTE RP 188; programmable phase alignment synchronizes video/audio sample boundaries.

Ethernet Switch/Router Timing

PCIe Gen 1–4 Clocking

Use Scenario: High-port-count 1/10 GbE switches requiring synchronous 125 MHz and 156.25 MHz clocks with sub-1 ps jitter.

IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter Ethernet reference clocks with independent voltage and format control.

Use Value: Eliminates four discrete oscillators; reduces board area by >60% while meeting IEEE 802.3 jitter masks via 0.7 ps RMS performance.

Use Scenario: Server motherboard with multiple PCIe slots requiring Gen 3/4 Common Clock and SRNS-compliant timing.

IC Role / Device Role / Timing Role: Primary clock source delivering 100 MHz differential HCSL clocks with PCIe Gen 4 Common Clock jitter compliance.

Use Value: Meets 0.15–0.45 ps RMS jitter requirement across all lanes; supports simultaneous Gen 3 SRNS and Gen 4 CC modes via register configuration.

Processor & FPGA Clocking

Broadcast Video/Audio Timing

Use Scenario: Heterogeneous SoC platform with ARM CPU, GPU, DDR4 memory, and FPGA fabric needing distinct clock domains.

IC Role / Device Role / Timing Role: Centralized clock synthesizer generating 500 MHz (CPU), 300 MHz (GPU), 1333 MHz (DDR4), and 100 MHz (FPGA logic) from one reference.

Use Value: Independent MultiSynth™ blocks enable integer/fractional synthesis per domain; eliminates inter-clock crosstalk via isolated output buffers.

Use Scenario: SMPTE ST 2082/2081 video router requiring SMPTE 2082 (270 MHz), ST 2081 (12 Gbps), and AES3 audio (48 kHz) clocks.

IC Role / Device Role / Timing Role: Broadcast-grade timing IC delivering ultra-low-jitter 270 MHz LVPECL and 48 kHz CMOS clocks from a single 27 MHz crystal.

Use Value: 0.7 ps RMS jitter ensures compliance with SMPTE RP 188; programmable phase alignment synchronizes video/audio sample boundaries.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05089-GM	Higher integration: 8 outputs, integrated jitter cleaner, lower 0.35 ps RMS jitter; requires external 100 MHz reference for optimal performance	Targeted at 5G infrastructure and high-end compute where jitter margin is critical and board space permits larger 32-QFN	Select when sub-0.4 ps RMS jitter and >4 outputs are required; not drop-in due to different pinout and register map
ICS853S01AGI-01LFT	Fixed-frequency, non-programmable quad LVDS generator; 1.2 ps RMS jitter; no I²C interface or spread spectrum	Suitable only for static clock trees where frequencies never change post-BOM	Choose for cost-sensitive, low-complexity designs with unchanging clock requirements; lacks Si5338A-B05001-GM's any-frequency flexibility

Compared with Si5332A-D05089-GM and ICS853S01AGI-01LFT, SI5338A-B05001-GM uniquely balances field-programmability, PCIe Gen 4 compliance, and compact 24-QFN packaging-making it optimal for mid-tier networking and embedded systems requiring design flexibility without over-engineering.

Availability

SI5338A-B05001-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 1–4 clocking, and processor/FPGA clocking requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338A-B05001-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for communications, automotive, and industrial markets.

The Si5338 family was designed specifically for high-performance, multi-protocol clock generation in data center, telecom, and broadcast equipment-emphasizing low jitter, I²C configurability, and PCIe/Ethernet compliance.

FAQ

What is the maximum output frequency supported by SI5338A-B05001-GM?

The SI5338A-B05001-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs and 350 MHz on SSTL/HSTL outputs. For frequencies above 350 MHz, only two unique outputs may operate simultaneously (Fvco/4 and Fvco/6), as defined in the Synthesis Stages section of the datasheet. All outputs maintain 0.7 ps RMS typical jitter within their respective ranges.

Does SI5338A-B05001-GM support PCIe Gen 4 Common Clock mode?

Yes, SI5338A-B05001-GM is explicitly compliant with PCIe Gen 4 Common Clock mode, delivering 0.15–0.45 ps RMS jitter when configured with 100 MHz HCSL outputs and a PLL bandwidth of 2–5 MHz. This meets the PCI-Express Base Specification 4.0 rev. 0.5 requirement for total jitter under the specified measurement conditions.

Can SI5338A-B05001-GM generate different output voltages on each channel?

Yes, SI5338A-B05001-GM provides four independent output supply rails (VDDO0–VDDO3), each configurable from 1.4 V to 3.63 V. This allows simultaneous LVPECL (2.5 V), LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs - enabling direct interfacing with mixed-voltage FPGAs, processors, and SerDes without external level shifters.

How is SI5338A-B05001-GM programmed in-system?

SI5338A-B05001-GM is programmed via its I²C/SMBus-compatible serial interface (SCL/SDA pins) operating at standard (100 kHz) or fast-mode (400 kHz) speeds. Configuration is simplified using Skyworks' ClockBuilder Pro software, which generates register maps and validates settings against jitter and timing constraints before deployment.

What crystal frequency ranges does SI5338A-B05001-GM support?

SI5338A-B05001-GM supports external crystals from 8 to 30 MHz, segmented into four validated bands: 8–11 MHz, 11–19 MHz, 19–26 MHz, and 26–30 MHz. Each band specifies recommended load capacitance (17–19 pF) and maximum ESR (75–300 Ω) to ensure reliable startup and low-phase-noise operation per AN360 guidelines.

SI5338A-B05001-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B05001-GM FAQ

1.How can I place an order for SI5338A-B05001-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B05001-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B05001-GM reliable?

The price and inventory of SI5338A-B05001-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B05001-GM is usually 5 days.

3.What payment methods are accepted for SI5338A-B05001-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B05001-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B05001-GM?

SI5338A-B05001-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B05001-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B05001-GM?

For technical support, including SI5338A-B05001-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B05001-GM requirements.

6.How does Aetrix verify that SI5338A-B05001-GM is sourced from the original manufacturer or authorized distributors?

All SI5338A-B05001-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B05001-GM meets industry standards.

7.What is the process for return or replacement of SI5338A-B05001-GM?

All SI5338A-B05001-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B05001-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B05001-GM part is unused and in its original packaging.

Return procedure for SI5338A-B05001-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…