Skyworks Solutions Inc. SI5338A-B05144-GM
- Part No.:
- SI5338A-B05144-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338A-B05144-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:1,143
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338A-B05144-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and MultiSynth™ frequency synthesis supporting 0.16–710 MHz output ranges across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in Ethernet switch/router and FPGA clocking systems.
For engineers reviewing the SI5338A-B05144-GM datasheet, SI5338A-B05144-GM pinout, SI5338A-B05144-GM application, or SI5338A-B05144-GM equivalent, key selection considerations include its 24-QFN package, independent per-output voltage (1.5/1.8/2.5/3.3 V), ±20 ps phase step resolution, 1 ppm frequency increment/decrement capability, and support for external crystal (8–30 MHz), CMOS (5–200 MHz), or differential (5–710 MHz) reference inputs.
Technical Context
The SI5338A-B05144-GM implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to one of six input sources, followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output with integer or fractional division. Each output path includes programmable slew rate control, spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz), and loss-of-lock/loss-of-signal alarms.
Its I²C/SMBus interface enables full register configuration including per-output format, voltage, termination, phase offset (±45 ns), and frequency tuning via PINC/FDEC pins or software. The device operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw and supports –40 to +85 °C industrial temperature range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements at 125 MHz output |
| Output Frequency Range | 0.16–710 MHz - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, Fibre Channel 1.0625 GHz (via /2 divider) |
| Input Reference Support | 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, 5–710 MHz differential - enables flexible system clock tree design |
| Output Driver Flexibility | Up to 4 differential (LVPECL/LVDS/HCSL/CML) or 8 single-ended (CMOS/SSTL/HSTL) outputs - eliminates need for external level translators |
| Core Supply Voltage | 1.8 V / 2.5 V / 3.3 V - compatible with modern low-voltage SoC/FPGA power domains |
| Package | 24-pin QFN, 4 × 4 mm - space-efficient footprint for dense PCB layouts |
| Operating Temperature | –40 to +85 °C - qualified for industrial and telecom line card environments |
Pinout & Package
SI5338A-B05144-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is top-left corner (IN1), and pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential Input Pairs | Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination |
| IN3, IN4 | Single-Ended Input | Support 5–200 MHz CMOS-level clocks; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A/CLK0B to CLK3A/CLK3B | Differential Output Pairs | Four independent output drivers; each configurable as LVPECL/LVDS/HCSL/CML with dedicated VDDOx supply |
| VDDO0–VDDO3 | Output Buffer Supplies | Independent 1.5/1.8/2.5/3.3 V supplies per output bank - enable mixed-voltage clock distribution |
| VDD | Core Supply | Single 1.8/2.5/3.3 V supply for PLL and logic; PSRR optimized for clean timing operation |
| SCL/SDA | I²C Interface | Standard SMBus-compatible serial interface (up to 400 kHz); supports write-only programming and readback of status registers |
| INTR | Interrupt Output | Open-drain alarm signal indicating loss-of-lock, loss-of-signal, or NVM error |
| RSVD_GND | Reserved Ground | Internal test pin; must be connected to GND per layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Synthesis | Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs without external crystals |
| PCIe Gen 3 SRNS Compliance | 0.11–0.32 ps RMS jitter in Separate Reference mode - satisfies stringent SerDes clocking requirements |
| Per-Output Phase Adjustment | ±45 ns range with <20 ps step resolution - enables precise skew management across multi-lane interfaces |
| Glitchless Frequency Tuning | 1 ppm incremental/decremental steps via PINC/FDEC pins - allows real-time clock rate adaptation without output interruption |
| Spread Spectrum Control | Configurable 0.5–5.0% down-spread at 33–63 kHz on any output - reduces EMI in noise-sensitive applications |
Applications
| Processor and FPGA Clocking | PCIe Gen 1–4 Timing |
|---|---|
Use Scenario: Providing multiple synchronized clocks to heterogeneous SoCs, FPGAs, and ASICs in compute-accelerator boards. IC Role / Device Role / Timing Role: Quad-output clock generator delivering independent 100 MHz PCIe REFCLK, 125 MHz Ethernet, 156.25 MHz SerDes, and 200 MHz system clock. Use Value: Eliminates four discrete oscillators and external fanout buffers while maintaining sub-1 ps jitter across all domains. | Use Scenario: Generating compliant reference clocks for PCIe root complexes, switches, and endpoint devices. IC Role / Device Role / Timing Role: Common Clock source meeting PCIe Gen 4 jitter spec (0.15–0.45 ps RMS) and SRNS mode for Gen 3. Use Value: Single-device solution certified for PCIe Base Spec 4.0 rev 0.5, reducing BOM count and layout complexity. |
| Ethernet Switch/Routing | Broadcast Video/Audio Timing |
Use Scenario: Synchronizing packet processing, switching fabric, and PHY interfaces in 1/10 GbE line cards. IC Role / Device Role / Timing Role: Low-jitter clock source for 125 MHz (1 GbE), 156.25 MHz (10 GbE), and 312.5 MHz (25 GbE via /2) lanes. Use Value: Meets IEEE 802.3 jitter limits (0.7 ps RMS GbE random jitter) with deterministic jitter <10 ps pk-pk. | Use Scenario: Distributing frame-synchronized clocks across SDI, HDMI, and audio codecs in broadcast encoders. IC Role / Device Role / Timing Role: Any-frequency generator producing 27 MHz (SDI), 74.25 MHz (HD), 148.5 MHz (3G-SDI), and 48 kHz audio word clocks. Use Value: Replaces multiple crystal oscillators with one programmable device, simplifying inventory and enabling field firmware updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B05145-GM | Same silicon; factory-programmed with different default NVM configuration (output frequencies, formats, and voltages pre-set) | Pre-configured for alternate reference input (e.g., 25 MHz crystal vs. 19.44 MHz) and output set (e.g., 156.25/125/100/25 MHz) | Select when requiring identical functionality with factory-tuned settings for specific platform integration |
| LMK04832ISQE/NOPB | Two PLLs + eight outputs; higher power (120 mA), larger 48-QFN package; supports JESD204B deterministic latency | Targeted at high-speed data converter timing with ultra-low skew and deterministic delay; not PCIe SRNS-compliant | Choose for JESD204B systems requiring sub-100 ps channel-to-channel skew and programmable delay, not for PCIe or Ethernet clock trees |
Compared with Si5338A-B05145-GM, SI5338A-B05144-GM offers identical silicon performance but distinct factory NVM settings; versus LMK04832ISQE/NOPB, SI5338A-B05144-GM provides lower power, smaller footprint, and PCIe-specific compliance at the expense of JESD204B features and output count.
Availability
SI5338A-B05144-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 timing, and broadcast video/audio timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338A-B05144-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line delivers programmable, low-jitter clock generation for high-speed digital systems, targeting applications where precision timing, flexibility, and space-constrained packaging are critical - especially in networking, computing, and communications infrastructure.
FAQ
What reference clock inputs does the SI5338A-B05144-GM support?
The SI5338A-B05144-GM supports six reference inputs: differential (IN1/IN2, IN5/IN6) from 5–710 MHz, single-ended CMOS (IN3/IN4) from 5–200 MHz, SSTL/HSTL (IN3/IN4) from 5–350 MHz, and external crystal (8–30 MHz) on IN1/IN2. All inputs are selectable via I²C configuration, and the device automatically detects valid clock presence using loss-of-signal circuitry. SI5338A-B05144-GM requires no external components for crystal drive beyond standard load capacitors.
Does the SI5338A-B05144-GM meet PCIe Gen 4 timing specifications?
Yes, the SI5338A-B05144-GM meets PCIe Gen 4 Common Clock jitter requirements with 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines. It achieves this using a 2–4 MHz PLL bandwidth and CDR=10 MHz filter setting. SI5338A-B05144-GM also complies with PCIe Gen 3 SRNS mode (0.11–0.32 ps RMS) and Gen 1/2/3 Common Clock specs, verified using the Skyworks PCIe Clock Jitter Tool.
How many output formats can the SI5338A-B05144-GM generate simultaneously?
The SI5338A-B05144-GM supports simultaneous generation of up to four differential outputs (LVPECL/LVDS/HCSL/CML) or eight single-ended outputs (CMOS/SSTL/HSTL), or any combination thereof - e.g., two LVDS pairs + two CMOS clocks. Each output driver is independently configurable for format, voltage (1.5/1.8/2.5/3.3 V), termination, and slew rate. SI5338A-B05144-GM does not require external level-shifting components for mixed-format clock trees.
Can the SI5338A-B05144-GM operate in clock buffer (PLL bypass) mode?
Yes, the SI5338A-B05144-GM supports clock buffer mode where the input clock passes directly to selected outputs with minimal additive jitter (0.165 ps RMS, 12 kHz–20 MHz). In this mode, the PLL is disabled, propagation delay is 2.5–4 ns, and loss-of-signal detection remains functional above 5 MHz. SI5338A-B05144-GM retains full I²C configurability for output format, voltage, and enable control even in bypass mode.
What software tools are available to configure the SI5338A-B05144-GM?
Skyworks ClockBuilder Pro is the official GUI-based configuration tool for SI5338A-B05144-GM, enabling point-and-click setup of input references, output frequencies, formats, voltages, spread spectrum, and phase offsets. It generates I²C register maps and supports NVM programming via USB adapter. SI5338A-B05144-GM configuration files can be exported for integration into production programming workflows or embedded host initialization sequences.
SI5338A-B05144-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338A-B05144-GM FAQ
1.How can I place an order for SI5338A-B05144-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338A-B05144-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338A-B05144-GM reliable?
The price and inventory of SI5338A-B05144-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B05144-GM is usually 5 days.
3.What payment methods are accepted for SI5338A-B05144-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B05144-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338A-B05144-GM?
SI5338A-B05144-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338A-B05144-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338A-B05144-GM?
For technical support, including SI5338A-B05144-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B05144-GM requirements.
6.How does Aetrix verify that SI5338A-B05144-GM is sourced from the original manufacturer or authorized distributors?
All SI5338A-B05144-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B05144-GM meets industry standards.
7.What is the process for return or replacement of SI5338A-B05144-GM?
All SI5338A-B05144-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B05144-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338A-B05144-GM part is unused and in its original packaging.
Return procedure for SI5338A-B05144-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338A-B05144-GM Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

