Skyworks Solutions Inc. SI5338A-B05145-GM
- Part No.:
- SI5338A-B05145-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338A-B05145-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:1,088
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Product details
Overview
SI5338A-B05145-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats. It serves as a drop-in replacement for up to four crystal oscillators in high-speed serial interface timing.
For engineers reviewing the SI5338A-B05145-GM datasheet, SI5338A-B05145-GM pinout, SI5338A-B05145-GM application, or SI5338A-B05145-GM equivalent, key selection considerations include its 24-QFN package, 4× differential output capability, programmable per-output voltage (1.5/1.8/2.5/3.3 V), independent phase/frequency adjustment (±45 ns / 1 ppm steps), and spread-spectrum control (0.5–5.0% down-spread).
Technical Context
The SI5338A-B05145-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks. Each output path includes configurable dividers (R/M/P), selectable output drivers, and dedicated voltage supplies (VDDO0–VDDO3).
It supports flexible reference inputs - external 8–30 MHz crystal, CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) - and enables zero-delay mode via external feedback. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring over the I²C/SMBus interface.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | 4 differential clock outputs (CLK0A/B through CLK3A/B); supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL |
| Frequency range | 0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 3 SRNS and Gen 4 Common Clock specs |
| Supply voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver |
| Input references | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating temp | –40 °C to +85 °C ambient, qualified for industrial applications |
Pinout & Package
The SI5338A-B05145-GM is housed in a 24-lead QFN package (4 mm × 4 mm) with an exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1/IN2, IN5/IN6 | Differential reference inputs | Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination |
| IN3/IN4 | Single-ended reference inputs | Support CMOS/SSTL/HSTL signals (5–350 MHz); internally biased, no external pull-up needed |
| CLK0A/CLK0B – CLK3A/CLK3B | Differential clock outputs | Four independent pairs; each configurable for format, voltage, enable, and phase offset |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5/1.8/2.5/3.3 V rails per output pair; decoupling required per pin |
| VDD | Core supply | Single 1.8/2.5/3.3 V core rail; PSRR optimized for low-noise operation |
| SCL/SDA | I²C interface | Standard SMBus-compatible 100/400 kHz interface; supports write-protection and register locking |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock, loss-of-signal, or configuration error |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Enables true zero-ppm accuracy on all four outputs without external VCXO or loop filter components |
| Per-output voltage control | Each of four output banks powered independently (1.5/1.8/2.5/3.3 V), eliminating level-shifting ICs in mixed-voltage systems |
| Glitchless frequency tuning | Real-time ±1 ppm step adjustments via PINC/FDEC pins or I²C, with no output interruption or phase discontinuity |
| Programmable phase offset | ±45 ns fine-grained phase alignment per output (20 ps steps), critical for skew-sensitive SerDes interfaces |
| Spread spectrum control | Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI peak emissions |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch Synchronization |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four identical, low-jitter 100 MHz HCSL clocks with matched propagation delay and <100 ps inter-output skew. Use Value: Meets PCIe Gen 4 Common Clock TJ < 33.6 ps pk-pk requirement while enabling single-device consolidation of four discrete oscillators. | Use Scenario: Generating 125 MHz and 156.25 MHz clocks for 10 GbE PHYs and packet processors on a telecom line card. IC Role / Device Role / Timing Role: Frequency translator converting a 25 MHz crystal input into two independent, jitter-clean Ethernet rates with independent voltage control (1.8 V for PHY, 3.3 V for processor). Use Value: Eliminates need for separate clock synthesizers and level shifters; achieves <0.7 ps RMS jitter compliant with IEEE 802.3bj. |
| Broadcast Video Frame Sync | FPGA-Based Video Processing |
Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI transmitters, receivers, and video processors in a broadcast router. IC Role / Device Role / Timing Role: Any-frequency clock generator supporting SMPTE ST 2081–10/ST 2082–10 timing with programmable phase offsets for frame alignment. Use Value: Enables precise sub-nanosecond phase alignment across video paths without manual trimming or external delay lines. | Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR3 interface clock, and 100 MHz peripheral clock to a Xilinx Kintex-7 FPGA in a medical imaging subsystem. IC Role / Device Role / Timing Role: Configurable clock source providing three distinct frequencies with independent CMOS/LVDS formats and voltage levels matching FPGA I/O banks. Use Value: Reduces BOM count by replacing three discrete clock ICs; supports dynamic reconfiguration via I²C during FPGA partial reconfiguration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05145-GM | Higher integration: integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs, but larger 32-QFN package | Preferred where board space allows and ultra-low jitter is mandatory (e.g., 400G optical modules) | Select when needing better jitter performance and built-in crystal; avoid if footprint or cost sensitivity requires minimal size |
| ICS8430I-01T | Fixed-frequency (non-programmable), 4-output LVDS clock fanout buffer; no synthesis, no I²C, 1.2 ps RMS jitter | Used only for simple clock distribution where input frequency matches all outputs exactly | Select only for static, low-cost clock fanout; not suitable for frequency translation or multi-format needs |
Compared with Si5332A-D05145-GM and ICS8430I-01T, the SI5338A-B05145-GM uniquely balances programmability, jitter performance, and compact 24-QFN packaging-making it optimal for space-constrained, multi-protocol designs requiring field-reconfigurable timing.
Availability
SI5338A-B05145-GM is available at Aetrix Electronics and suitable for PCIe switch timing, Ethernet synchronization, broadcast video genlock, and FPGA clocking applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5338A-B05145-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line was designed specifically for high-performance, software-configurable clock generation in multi-standard serial interface systems-including PCIe, Ethernet, Fibre Channel, and broadcast video-where flexibility, low jitter, and small footprint are critical.
FAQ
What is the maximum output frequency supported by the SI5338A-B05145-GM?
The SI5338A-B05145-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6), as defined in the synthesis architecture. All outputs maintain 0.7 ps RMS typical jitter within their respective rated ranges.
Does the SI5338A-B05145-GM support PCIe Gen 4 timing requirements?
Yes, the SI5338A-B05145-GM meets PCIe Gen 4 Common Clock specifications with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) and supports the required 2–4 MHz or 2–5 MHz PLL bandwidth settings. It is also compliant with PCIe Gen 3 SRNS and backward compatible with Gen 1/2/3 Common Clock modes.
Can the SI5338A-B05145-GM operate without an external crystal?
Yes - the SI5338A-B05145-GM accepts multiple reference sources: external 8–30 MHz crystal, CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) inputs. Crystal operation is optional; the device functions fully with any supported single-ended or differential clock input.
How is output voltage configured on the SI5338A-B05145-GM?
Each of the four output banks (CLK0, CLK1, CLK2, CLK3) has its own dedicated VDDOx supply pin (VDDO0–VDDO3). The output driver voltage is set by the voltage applied to that pin - supporting 1.5 V, 1.8 V, 2.5 V, or 3.3 V independently. No register configuration is required; voltage selection is hardware-defined per bank.
Is ClockBuilder Pro software required to configure the SI5338A-B05145-GM?
No - ClockBuilder Pro is optional but strongly recommended. The SI5338A-B05145-GM can be configured via standard I²C commands using any host microcontroller. ClockBuilder Pro simplifies register setup, validates configuration integrity, generates initialization code, and provides jitter simulation - significantly reducing bring-up time and risk of misconfiguration.
SI5338A-B05145-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338A-B05145-GM FAQ
1.How can I place an order for SI5338A-B05145-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338A-B05145-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338A-B05145-GM reliable?
The price and inventory of SI5338A-B05145-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B05145-GM is usually 5 days.
3.What payment methods are accepted for SI5338A-B05145-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B05145-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338A-B05145-GM?
SI5338A-B05145-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338A-B05145-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338A-B05145-GM?
For technical support, including SI5338A-B05145-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B05145-GM requirements.
6.How does Aetrix verify that SI5338A-B05145-GM is sourced from the original manufacturer or authorized distributors?
All SI5338A-B05145-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B05145-GM meets industry standards.
7.What is the process for return or replacement of SI5338A-B05145-GM?
All SI5338A-B05145-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B05145-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338A-B05145-GM part is unused and in its original packaging.
Return procedure for SI5338A-B05145-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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