Skyworks Solutions Inc. SI5338A-B05146-GM

Overview

SI5338A-B05146-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis. It delivers four independent, any-frequency differential or single-ended clocks (0.16–710 MHz), supports PCIe Gen 1–4 common clock and SRNS compliance, achieves 0.7 ps RMS typical phase jitter, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package for FPGA, processor, and high-speed serial interface timing.

For engineers reviewing the SI5338A-B05146-GM datasheet, SI5338A-B05146-GM pinout, SI5338A-B05146-GM application, or SI5338A-B05146-GM equivalent, key selection criteria include PCIe Gen 4 SRNS jitter compliance (0.15–0.45 ps RMS), independent per-output voltage configuration (1.5–3.3 V), 1 ppm frequency increment/decrement resolution, <20 ps phase step accuracy, and flexible input support (8–30 MHz crystal, 5–710 MHz differential).

Technical Context

The SI5338A-B05146-GM integrates a dual-stage PLL architecture: Stage 1 uses a VCO with programmable feedback divider (N) and reference dividers (R₀–R₃); Stage 2 employs four independent MultiSynth™ synthesizers (M₀–M₃) with fractional-N capability and P₁/P₂ output dividers. Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with configurable termination and voltage.

It features loss-of-signal and loss-of-lock monitoring, I²C/SMBus interface with register-based configuration, external feedback mode for zero-delay operation, and independent spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation) on any output. The device supports glitchless frequency tuning via dedicated PINC/FDEC pins and programmable initial phase offset (±45 ns).

Key Specifications

Pinout & Package

SI5338A-B05146-GM is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with Si5332A-D05146-GM and ICS8430I-01LG, the SI5338A-B05146-GM uniquely balances field-programmability, PCIe Gen 4 compliance, and mixed-signal output flexibility without integrated crystal overhead-making it optimal for mid-volume, multi-standard timing consolidation.

Availability

SI5338A-B05146-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10 GbE synchronization, broadcast video master clocking, and FPGA-based test equipment requiring stable component supply and long-term design-in support.

Supply support for SI5338A-B05146-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in multi-standard systems-enabling consolidation of discrete oscillators and buffers into a single, PCIe- and Ethernet-compliant timing IC.

FAQ

What is the maximum output frequency supported by the SI5338A-B05146-GM?

The SI5338A-B05146-GM supports differential output frequencies up to 710 MHz (LVPECL/LVDS/CML), 350 MHz (SSTL/HSTL), 250 MHz (HCSL), and 200 MHz (CMOS). Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6), as specified in the Si5338 datasheet Section 3.3. This capability enables direct clocking of high-speed SerDes lanes without external frequency multiplication.

Does the SI5338A-B05146-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338A-B05146-GM is explicitly compliant with PCIe Gen 4 SRNS requirements, delivering 0.11–0.32 ps RMS jitter under specified conditions (PLL bandwidth 2–4 MHz, CDR = 10 MHz). This is verified in Table 12 of the official Skyworks datasheet Rev. 1.6 and confirmed by measurement using the Skyworks PCIe Clock Jitter Tool.

Can the SI5338A-B05146-GM generate different output voltages on each clock bank?

Yes, the SI5338A-B05146-GM provides independent VDDO₀–VDDO₃ supplies, allowing each of its four output banks to be configured for 1.5 V, 1.8 V, 2.5 V, or 3.3 V operation. This enables direct interfacing with mixed-voltage components (e.g., 1.8 V FPGA I/O, 3.3 V microcontroller, 2.5 V PHY) without external level shifters or voltage translators.

How is the SI5338A-B05146-GM programmed, and is configuration retained after power cycle?

The SI5338A-B05146-GM is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software. Configuration is stored in one-time-programmable (OTP) non-volatile memory, ensuring that the device boots with the last programmed settings without requiring host initialization. Factory programming is also supported for turnkey deployment.

What input reference options does the SI5338A-B05146-GM support?

The SI5338A-B05146-GM accepts multiple input references: an 8–30 MHz fundamental-mode crystal (connected to IN1/IN2), a 5–200 MHz CMOS clock (IN3/IN4), a 5–350 MHz SSTL/HSTL signal (IN3/IN4), or a 5–710 MHz differential clock (IN1/IN2 or IN5/IN6). This flexibility eliminates dependency on specific oscillator types and simplifies reference sourcing across platforms.