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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B05146-GMR

Name: SI5338A-B05146-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B05146-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B05146-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B05146-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338A-B05146-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator using MultiSynth™ technology to synthesize independent any-frequency outputs (0.16–710 MHz) with 0 ppm precision. It delivers LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL outputs, supports PCIe Gen 1–4 common-clock and SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package for FPGA, processor, and high-speed serial interface timing.

For engineers reviewing the SI5338A-B05146-GMR datasheet, SI5338A-B05146-GMR pinout, SI5338A-B05146-GMR application, or SI5338A-B05146-GMR equivalent, key selection criteria include differential output jitter (0.7 ps RMS typ), four independently configurable output drivers, PCIe Gen 4 SRNS compliance, spread-spectrum control (0.5–5.0% down-spread), and phase/frequency increment/decrement capability (±45 ns / 1 ppm steps).

Technical Context

The SI5338A-B05146-GMR implements a two-stage synthesis architecture: a PLL-based Stage 1 (with 1.6 MHz loop bandwidth) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N dividers (Stage 2) per output. Each output driver supports format- and voltage-selectable signaling (1.5–3.3 V) and includes dedicated OEB, PINC/FINC, and INTR pins for real-time control and status monitoring.

It features on-chip OTP NVM for factory or field programming, external feedback mode for zero-delay operation, and dual alarm functions (loss-of-lock and loss-of-signal). The device supports both integer and fractional synthesis modes, with jitter performance validated per JEDEC 65 and PCIe Base Spec 4.0 rev. 0.5 for Gen 4 common-clock applications.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	Four differential clock outputs (CLK0A/B through CLK3A/B); supports up to eight single-ended clocks via configuration
Frequency range	0.16–710 MHz per output; supports two frequencies >350 MHz simultaneously (Fvco/4 and Fvco/6)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), measured at 125 MHz LVDS output with 25 MHz reference
PCIe compliance	Gen 1/2/3/4 Common Clock; Gen 3 SRNS compliant; Gen 4 jitter ≤0.45 ps RMS (PLL BW 2–5 MHz, CDR = 10 MHz)
Supply & power	1.8/2.5/3.3 V core (VDD); independent 1.4–3.63 V output buffers (VDDO0–VDDO3); 45 mA typical core current @100 MHz all outputs
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad; RoHS-compliant, halogen-free
Operating temp.	–40 °C to +85 °C ambient; junction temperature limited to 150 °C

Pinout & Package

SI5338A-B05146-GMR is housed in a 24-lead, 4 × 4 mm QFN package with wettable flanks and an exposed thermal pad (GND-connected). Pin 1 is top-left corner (IN1), with clockwise numbering. The package supports standard reflow per JEDEC J-STD-020 (peak 260 °C).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled differential clocks (5–710 MHz); require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH/VIL referenced to VDD
CLK0A–CLK3B	Differential output pairs	Four independent output channels; each pair (e.g., CLK0A/CLK0B) drives one differential clock
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output bank; set output logic level and drive strength
VDD	Core supply	1.8/2.5/3.3 V ± tolerance; powers PLL, synthesizers, and control logic
SCL, SDA	I²C interface	SMBus-compatible 2-wire serial bus (up to 400 kHz); used for register configuration and status readback
INTR	Interrupt output	Open-drain active-low signal indicating loss-of-lock or loss-of-signal events
OEB, PINC, FINC	Control inputs	Hardware-enable/disable outputs (OEB); pin-controlled phase/frequency increment/decrement (PINC/FINC)

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable true zero-ppm frequency accuracy on all outputs without external crystals
Flexible output configuration	Each output supports LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL formats with programmable voltage (1.5/1.8/2.5/3.3 V)
Glitchless frequency tuning	Hardware pin-controlled frequency increment/decrement in 1 ppm steps, with update time as low as 667 ns
Precision phase control	Independent phase adjustment per output with <20 ps step resolution and ±45 ns total range
Spread-spectrum clocking	Configurable SSC on any output: 0.5–5.0% spread depth, 33–63 kHz modulation rate, down-spread only
Status monitoring	Dedicated INTR pin reports loss-of-lock and loss-of-signal conditions with sub-10 ms detection latency

Applications

Ethernet Switch/Routing Timing	PCIe Gen 4 System Clocking
Use Scenario: High-density 10 GbE/25 GbE switch fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors. IC Role / Device Role / Timing Role: Primary quad-output clock source generating 156.25 MHz (10GbE), 125 MHz (SFP+), 100 MHz (CPU), and 25 MHz (management controller) from a single 25 MHz crystal. Use Value: Eliminates four discrete oscillators; enables deterministic inter-output skew (<100 ps) and PCIe Gen 4-compliant jitter (≤0.45 ps RMS) across all lanes.	Use Scenario: Server motherboard with dual CPU sockets and multiple PCIe Gen 4 x16 slots requiring common-reference clock distribution with strict jitter limits. IC Role / Device Role / Timing Role: PCIe Gen 4 Common Clock generator delivering four 100 MHz HCSL clocks - two for CPU root complexes and two for downstream switch/ASICs. Use Value: Meets PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS) with on-chip PLL optimization; supports hardware frequency margining via PINC/FINC pins during validation.
Broadcast Video/Audio Sync	FPGA-Based Signal Processing
Use Scenario: SMPTE 2110 IP video router needing precise 74.25 MHz (HD), 148.5 MHz (UHD), 27 MHz (SDI), and 32 kHz audio word clock synchronization. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating four independent broadcast-grade clocks from a single 10 MHz OCXO reference. Use Value: Achieves <0.7 ps RMS jitter on all outputs; supports programmable initial phase offset (–45 to +45 ns) for frame-aligned multi-channel sync.	Use Scenario: High-throughput radar or AI inference accelerator using Xilinx Versal or Intel Agilex FPGA with multiple clock domains (PL fabric, memory interfaces, transceivers). IC Role / Device Role / Timing Role: Configurable clock generator supplying 300 MHz (PL logic), 1600 MHz DDR4 PHY), 5 Gbps GTY transceiver refclk, and 100 MHz system management clock. Use Value: Enables single-device clock tree with independent voltage/format per domain; leverages external feedback mode for zero-delay buffering of critical paths.

Ethernet Switch/Routing Timing

PCIe Gen 4 System Clocking

Use Scenario: High-density 10 GbE/25 GbE switch fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors.

IC Role / Device Role / Timing Role: Primary quad-output clock source generating 156.25 MHz (10GbE), 125 MHz (SFP+), 100 MHz (CPU), and 25 MHz (management controller) from a single 25 MHz crystal.

Use Value: Eliminates four discrete oscillators; enables deterministic inter-output skew (<100 ps) and PCIe Gen 4-compliant jitter (≤0.45 ps RMS) across all lanes.

Use Scenario: Server motherboard with dual CPU sockets and multiple PCIe Gen 4 x16 slots requiring common-reference clock distribution with strict jitter limits.

IC Role / Device Role / Timing Role: PCIe Gen 4 Common Clock generator delivering four 100 MHz HCSL clocks - two for CPU root complexes and two for downstream switch/ASICs.

Use Value: Meets PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS) with on-chip PLL optimization; supports hardware frequency margining via PINC/FINC pins during validation.

Broadcast Video/Audio Sync

FPGA-Based Signal Processing

Use Scenario: SMPTE 2110 IP video router needing precise 74.25 MHz (HD), 148.5 MHz (UHD), 27 MHz (SDI), and 32 kHz audio word clock synchronization.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating four independent broadcast-grade clocks from a single 10 MHz OCXO reference.

Use Value: Achieves <0.7 ps RMS jitter on all outputs; supports programmable initial phase offset (–45 to +45 ns) for frame-aligned multi-channel sync.

Use Scenario: High-throughput radar or AI inference accelerator using Xilinx Versal or Intel Agilex FPGA with multiple clock domains (PL fabric, memory interfaces, transceivers).

IC Role / Device Role / Timing Role: Configurable clock generator supplying 300 MHz (PL logic), 1600 MHz DDR4 PHY), 5 Gbps GTY transceiver refclk, and 100 MHz system management clock.

Use Value: Enables single-device clock tree with independent voltage/format per domain; leverages external feedback mode for zero-delay buffering of critical paths.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05146-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated crystal option; larger 5 × 5 mm 32-QFN package	Targeted at systems requiring >4 outputs or sub-0.4 ps jitter; not pin-compatible with SI5338A-B05146-GMR	Select when scaling beyond four clocks or requiring tighter jitter; requires PCB redesign due to different footprint and pinout.
ICS8430I-01T	Fixed-frequency quad LVDS generator (no I²C programming); 0.9 ps RMS jitter; 3.3 V only; 32-TQFP package	Limited to pre-defined frequencies; no spread spectrum, phase/frequency tuning, or multi-format support	Choose only for cost-sensitive, fixed-frequency designs where programmability and flexibility are unnecessary.

Compared with Si5332A-D05146-GM and ICS8430I-01T, SI5338A-B05146-GMR uniquely balances programmability, jitter performance, and compact 4 × 4 mm footprint-making it optimal for space-constrained, multi-protocol systems requiring field-tunable timing without layout change.

Availability

SI5338A-B05146-GMR is available at Aetrix Electronics and suitable for Ethernet switching, PCIe Gen 4 server platforms, broadcast video infrastructure, and FPGA-based signal processing systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338A-B05146-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.

The SI5338 family was designed to replace multiple discrete oscillators in high-speed digital systems, enabling flexible, low-jitter clock generation for PCIe, Ethernet, broadcast, and FPGA applications with minimal board space and design effort.

FAQ

What is the primary function of the SI5338A-B05146-GMR?

The SI5338A-B05146-GMR is a quad-output, I²C-programmable clock generator that synthesizes four independent, any-frequency clocks (0.16–710 MHz) with 0 ppm precision using Skyworks' MultiSynth™ technology. It replaces up to four discrete oscillators while supporting PCIe Gen 1–4, Ethernet, broadcast, and FPGA timing requirements in a single 4 × 4 mm QFN package.

Does the SI5338A-B05146-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338A-B05146-GMR meets PCIe Gen 4 Common Clock jitter specifications (≤0.45 ps RMS, 12 kHz–20 MHz) when configured with appropriate PLL bandwidth (2–5 MHz) and CDR frequency (10 MHz). It is also SRNS-compliant for PCIe Gen 3 and validated per PCI-Express Base Specification 4.0 rev. 0.5.

Can the SI5338A-B05146-GMR generate different output formats simultaneously?

Yes, the SI5338A-B05146-GMR supports simultaneous LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL outputs across its four channels. Each output driver has independent VDDO supply (1.5/1.8/2.5/3.3 V) and format selection, enabling mixed-signal clock trees-for example, LVDS for FPGA I/O and HCSL for PCIe slots.

How is the SI5338A-B05146-GMR programmed and configured?

The SI5338A-B05146-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration includes output frequencies, formats, voltages, spread-spectrum settings, phase offsets, and alarm thresholds. Factory-programmed OTP NVM retains settings across power cycles.

What are the thermal and power characteristics of the SI5338A-B05146-GMR?

The SI5338A-B05146-GMR operates from –40 °C to +85 °C with θJA = 37 °C/W (still air). Core supply current is 45 mA typical at 100 MHz on all outputs with 25 MHz reference; output buffer current varies by format and frequency (e.g., ≤30 mA for LVPECL @710 MHz). Thermal pad must be soldered to PCB ground plane for reliable operation.

SI5338A-B05146-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B05146-GMR FAQ

1.How can I place an order for SI5338A-B05146-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B05146-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B05146-GMR reliable?

The price and inventory of SI5338A-B05146-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B05146-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B05146-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B05146-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B05146-GMR?

SI5338A-B05146-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B05146-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B05146-GMR?

For technical support, including SI5338A-B05146-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B05146-GMR requirements.

6.How does Aetrix verify that SI5338A-B05146-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B05146-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B05146-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B05146-GMR?

All SI5338A-B05146-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B05146-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B05146-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B05146-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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