Skyworks Solutions Inc. SI5338A-B05246-GMR

Overview

SI5338A-B05246-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency clocks (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338A-B05246-GMR datasheet, SI5338A-B05246-GMR pinout, SI5338A-B05246-GMR application, or SI5338A-B05246-GMR equivalent, key selection considerations include differential output jitter performance (0.7 ps RMS), PCIe Gen 4 SRNS compliance, independent per-output voltage control (1.5–3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with space-constrained PCB layouts.

Technical Context

The SI5338A-B05246-GMR integrates a dual-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) feeding a fractional-N MultiSynth™ synthesis engine. Each of its four output drivers operates independently with dedicated M/N/P dividers, enabling true zero-ppm frequency accuracy across all outputs without shared divider constraints.

It supports flexible input references - including 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential inputs - and provides independent output configuration per channel for format, voltage, phase offset (<20 ps step), and spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% spread).

Key Specifications

Pinout & Package

SI5338A-B05246-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 pinout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref 2), IN5/IN6 (differential ref 3), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5338A-B05289-GM, SI5338A-B05246-GMR offers full field programmability and broader input reference flexibility; compared with LMK04832RHAR, it trades absolute jitter floor for lower cost, smaller footprint, and simpler power design - making it optimal for high-volume networking and compute platforms.

Availability

SI5338A-B05246-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, broadcast video sync generation, and FPGA-based telecom line card applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across manufacturing lots.

Supply support for SI5338A-B05246-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.

The Si5338 product line was designed specifically for high-density, multi-protocol serial interface timing - enabling consolidation of discrete oscillators and buffers in networking, computing, and communications systems while maintaining sub-picosecond jitter performance.

FAQ

What is the default factory configuration of the SI5338A-B05246-GMR?

The SI5338A-B05246-GMR ships with a blank NVM and no preloaded configuration. It requires initialization via I²C using ClockBuilder Pro software or custom firmware to define output frequencies, formats, and voltage settings before first use. Unlike factory-programmed variants (e.g., Si5338A-B05289-GM), this part offers full field programmability from power-on reset.

Does the SI5338A-B05246-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338A-B05246-GMR is explicitly validated for PCIe Gen 4 SRNS operation with 0.11–0.32 ps RMS jitter (typ/max) when configured with a 2–5 MHz PLL bandwidth and 10 MHz CDR. This compliance is documented in Skyworks' Si5338 datasheet Rev. 1.6, Table 12, and verified using the Skyworks PCIe Clock Jitter Tool.

Can the SI5338A-B05246-GMR generate four different frequencies simultaneously above 350 MHz?

No. While the SI5338A-B05246-GMR supports up to 710 MHz per output, only two unique frequencies above 350 MHz can be generated simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency division constraints. Higher-frequency outputs must share these two synthesis paths, limiting concurrent high-frequency diversity.

What is the maximum output current per VDDO pin on the SI5338A-B05246-GMR?

Each VDDO pin (VDDO0–VDDO3) supports up to 30 mA total output buffer current when driving LVPECL at 710 MHz, or up to 20 mA for HCSL at 250 MHz. The actual current depends on output format, frequency, and load; full specifications are detailed in Table 3 of the Si5338 datasheet Rev. 1.6 under "Output Buffer Supply Current".

How does the SI5338A-B05246-GMR handle loss-of-signal detection on its reference inputs?

The SI5338A-B05246-GMR provides loss-of-signal (LOS) detection on all six reference inputs (IN1–IN6) with programmable thresholds. Detection time is 2.6–5 µs (typ/max), and release time is 0.01–1 µs. An interrupt (INTR pin) asserts when LOS occurs, and status is readable via I²C register 0x000D, enabling real-time fault monitoring in redundant clock architectures.