Skyworks Solutions Inc. SI5338A-B05317-GMR

Overview

SI5338A-B05317-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ PLL architecture to synthesize independent frequencies up to 710 MHz on four differential outputs with 0 ppm precision, 0.7 ps RMS phase jitter (typ), and PCIe Gen 1–4 Common Clock & Gen 3 SRNS compliance - deployed in Ethernet switches, FPGA clocking, and PCIe-based storage systems.

For engineers reviewing the SI5338A-B05317-GMR datasheet, SI5338A-B05317-GMR pinout, SI5338A-B05317-GMR application, or SI5338A-B05317-GMR equivalent, key selection considerations include its 4× independent output voltage control (1.5/1.8/2.5/3.3 V), flexible input support (8–30 MHz crystal, 5–710 MHz differential), and glitchless frequency adjustment in 1 ppm steps via I²C or pin control.

Technical Context

The SI5338A-B05317-GMR integrates two synthesis stages: a high-stability PLL (1.6 MHz loop bandwidth) with fractional-N MultiSynth™ dividers per output, enabling integer- or fractional-mode synthesis across four independent output drivers. Each output path includes programmable slew rate, amplitude, and format selection without shared divider constraints.

It supports external feedback for zero-delay mode, loss-of-lock and loss-of-signal alarms, and independent phase offset (±45 ns, <20 ps step resolution) and spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation) on any output - all configurable via I²C/SMBus interface with OTP NVM storage.

Key Specifications

Pinout & Package

SI5338A-B05317-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5332A-D05317-GM, SI5338A-B05317-GMR offers lower cost and smaller footprint for 4-output systems; compared with ICS8430I-01T, it delivers full field reprogrammability and jitter headroom for next-gen PCIe and Ethernet standards.

Availability

SI5338A-B05317-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 add-in cards, and broadcast video timing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338A-B05317-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed digital systems - designed specifically to replace multiple discrete oscillators and simplify timing architecture in PCIe, Ethernet, and FPGA-based platforms.

FAQ

What is the maximum output frequency supported by SI5338A-B05317-GMR in LVPECL mode?

The SI5338A-B05317-GMR supports up to 710 MHz in LVPECL output mode, verified per Table 6 of the official Skyworks datasheet Rev. 1.6. This applies when using differential outputs with proper 100 Ω termination and VDDO ≥ 2.5 V. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) due to internal VCO constraints.

Does SI5338A-B05317-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338A-B05317-GMR meets PCIe Gen 4 Common Clock jitter requirements with ≤0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines - including PLL bandwidth setting of 2–4 MHz and CDR = 10 MHz. This is confirmed in Table 12 of the Rev. 1.6 datasheet under "PCIe Gen 4, Common Clock" test condition.

Can SI5338A-B05317-GMR generate different output voltages on each driver?

Yes, SI5338A-B05317-GMR provides independent VDDO0–VDDO3 pins enabling distinct output supply voltages per driver bank: 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows direct interfacing with mixed-voltage devices (e.g., 1.8 V FPGA I/O and 3.3 V legacy ASICs) without level shifters - confirmed in Features section and Table 1 of the datasheet.

How is SI5338A-B05317-GMR programmed, and what tools are required?

SI5338A-B05317-GMR is programmed via I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which generates configuration files and supports real-time register editing. The device includes OTP NVM to retain settings after power cycle. No external programmer is needed - standard microcontroller GPIO or evaluation board with I²C capability suffices.

What is the phase jitter performance of SI5338A-B05317-GMR at 125 MHz output?

At 125 MHz output with 25 MHz crystal reference, SI5338A-B05317-GMR achieves 0.7 ps RMS phase jitter (typical) over 12 kHz–20 MHz integration bandwidth, as specified in Table 12 of the Rev. 1.6 datasheet. This value applies to LVDS, HCSL, LVPECL, or CML outputs with low-noise differential input and optimal layout practices.