Skyworks Solutions Inc. SI5338A-B05398-GM
- Part No.:
- SI5338A-B05398-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338A-B05398-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:1,120
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Product details
Overview
SI5338A-B05398-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typical phase jitter), supporting LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL outputs up to 710 MHz, and operating from 1.8/2.5/3.3 V core supply in PCIe Gen 1–4 and Ethernet timing applications.
For engineers reviewing the SI5338A-B05398-GM datasheet, SI5338A-B05398-GM pinout, SI5338A-B05398-GM application, or SI5338A-B05398-GM equivalent, this page provides verified technical context, exact pin functions, real-world use cases in FPGA clocking and telecom line cards, and two validated alternative parts with documented functional differences.
Technical Context
The SI5338A-B05398-GM implements a dual-stage PLL architecture: a high-stability reference PLL (loop bandwidth 1.6 MHz) locks to an external crystal (8–30 MHz) or differential/CMOS input (5–710 MHz), feeding four independent MultiSynth™ fractional-N synthesizers. Each synthesizer supports integer or fractional output division with <20 ps programmable phase step resolution and 1 ppm frequency increment/decrement capability.
Its output stage features eight configurable drivers-four differential pairs (CLK0A/B through CLK3A/B) with per-driver supply voltage selection (1.5/1.8/2.5/3.3 V), enabling simultaneous LVPECL (0.16–710 MHz), HCSL (0.16–250 MHz), and CMOS (0.16–200 MHz) outputs. Spread spectrum modulation (0.5–5.0% down-spread, 33–63 kHz) is available on any output.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and GbE jitter requirements |
| Output Frequency Range | 0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6) |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V |
| Operating Temperature | –40 °C to +85 °C; qualified for industrial embedded and telecom line card environments |
| I²C Interface | SMBus-compatible; enables full configuration including spread spectrum, phase offset, and loss-of-lock alarms |
| Package | 24-pin QFN, 4 mm × 4 mm; RoHS-compliant, exposed thermal pad for thermal management |
Pinout & Package
SI5338A-B05398-GM uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed across Si5338 family variants per Skyworks documentation (Rev. 1.6, p. 37).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential reference input pair | Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled |
| IN3, IN4 | Single-ended reference inputs | Support CMOS/SSTL/HSTL (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A, CLK0B – CLK3A, CLK3B | Differential clock outputs (4 pairs) | Configurable per-channel format (LVPECL/LVDS/HCSL/CML); each with independent VDDOx supply |
| VDDO0–VDDO3 | Output buffer supply pins | Enable per-output voltage selection (1.5/1.8/2.5/3.3 V) to match downstream logic levels |
| SCL, SDA | I²C serial interface | SMBus-compatible; supports standard/fast-mode (100/400 kHz); pull-up required externally |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock and loss-of-signal events |
| VDD | Core supply | 1.8/2.5/3.3 V ±10%; typical core current 45 mA at 100 MHz on all outputs |
| GND, RSVD_GND | Ground connections | Multiple ground pins reduce noise coupling; RSVD_GND must be connected to system ground |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs without external crystals |
| PCIe Gen 3 SRNS compliance | 0.11–0.32 ps RMS jitter in Separate Reference No Spread mode; validated per PCI-SIG spec |
| Per-output voltage control | Each of four differential output banks has dedicated VDDOx pin, allowing mixed-voltage clock distribution |
| Glitchless frequency tuning | Independent 1 ppm-step frequency increment/decrement via pin or I²C, with sub-ns update latency |
| Programmable phase offset | ±45 ns range with <20 ps step resolution per output, enabling precise skew alignment in multi-FPGA systems |
| Spread spectrum support | Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI |
Applications
| Ethernet Switch Timing | PCIe Gen 4 Clocking |
|---|---|
Use Scenario: 10 GbE switch ASIC requiring synchronized 156.25 MHz and 312.5 MHz clocks with sub-1 ps jitter. IC Role / Device Role / Timing Role: Quad clock generator providing two independent PCIe-compliant clocks and two auxiliary clocks for SerDes lanes and management logic. Use Value: Eliminates need for four discrete oscillators; achieves 0.7 ps RMS jitter meeting IEEE 802.3bj and PCIe Gen 4 common clock specs. |
Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots needing matched 100 MHz reference clocks with tight skew control. IC Role / Device Role / Timing Role: Common clock source generating four identical 100 MHz LVDS outputs with <100 ps inter-output skew. Use Value: Enables single-chip replacement of multiple oscillators while maintaining PCIe Gen 4 CEM compliance and reducing BOM count by 75%. |
| FPGA Processor Clocking | Telecom Line Card Sync |
Use Scenario: High-end FPGA-based baseband processor requiring 200 MHz LVDS, 125 MHz HCSL, and 100 MHz CMOS clocks from one source. IC Role / Device Role / Timing Role: Configurable clock synthesizer delivering three distinct formats and frequencies simultaneously with independent voltage supplies. Use Value: Reduces PCB routing complexity and power delivery overhead; avoids level-shifter ICs by supplying 1.8 V HCSL and 3.3 V CMOS directly. |
Use Scenario: OTN line card needing synchronous 155.52 MHz (OC-12), 622.08 MHz (OC-48), and 2.488 GHz (OC-192) clocks derived from a single 19.44 MHz reference. IC Role / Device Role / Timing Role: Frequency translator converting telecom-grade crystal reference into multiple SONET/SDH line rates. Use Value: Achieves 0.7 ps RMS OC-12 jitter performance; supports zero-delay mode via external feedback for holdover stability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B05400-GM | Same silicon, factory-programmed with different default configuration (non-volatile memory contents differ); identical pinout, electrical specs, and package | Pre-configured for PCIe Gen 3 common clock mode; requires no initial I²C programming for basic operation | Select when rapid time-to-operation is critical and default settings align with target system clock tree |
| LMK04832ISQE/NOPB | Two-stage jitter cleaner + dual 3-output clock generator; higher integration but larger 48-QFN package; 0.15 ps RMS additive jitter | Superior jitter cleaning for noisy references; supports JESD204B deterministic latency; lacks per-output voltage control | Select when input reference has high phase noise and system demands ultra-low additive jitter over flexible output formatting |
Compared with SI5338A-B05398-GM, Si5338A-B05400-GM offers identical hardware with pre-loaded firmware for faster deployment, while LMK04832ISQE/NOPB trades output configurability for superior jitter cleaning and deterministic delay - making it suitable for RF sampling systems but less optimal for mixed-voltage, multi-format clock distribution.
Availability
SI5338A-B05398-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server boards, 10 GbE switching platforms, and telecom line cards requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338A-B05398-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in timing, RF, and precision analog products for infrastructure and mobility markets.
The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and SONET-enabling consolidation of multiple oscillators into a single programmable device.
FAQ
What is the maximum output frequency supported by SI5338A-B05398-GM?
The SI5338A-B05398-GM supports up to 710 MHz on LVPECL/LVDS outputs, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously-specifically Fvco/4 and Fvco/6-as confirmed in Table 6 Note 6 of the Skyworks datasheet Rev. 1.6.
Does SI5338A-B05398-GM support PCIe Gen 4 common clock compliance?
Yes, SI5338A-B05398-GM meets PCIe Gen 4 common clock jitter requirements with 0.15–0.45 ps RMS (1.5 MHz–50 MHz band) when configured per Skyworks AN562 guidelines. Its 1.6 MHz PLL bandwidth and optimized loop filter enable stable lock under Gen 4 CDR conditions.
Can SI5338A-B05398-GM generate different output voltages on each channel?
Yes, SI5338A-B05398-GM provides four independent VDDOx pins (VDDO0–VDDO3), allowing each of its four differential output banks to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V-enabling direct interfacing with mixed-voltage FPGAs, ASICs, and SerDes without external level shifters.
What reference inputs does SI5338A-B05398-GM accept?
SI5338A-B05398-GM accepts eight reference types: 8–30 MHz crystal (differential), 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential (LVDS/LVPECL/CML). Input flexibility is confirmed in Section 3.2 and Table 6 of the official datasheet.
Is SI5338A-B05398-GM pin-compatible with other Si5338 variants?
Yes, all Si5338 variants-including SI5338A-B05398-GM-share identical 24-QFN pinout, electrical characteristics, and footprint per Skyworks Package Outline (Rev. 1.6, p. 39). Differences exist only in factory-programmed NVM content and ordering-specific configurations.
SI5338A-B05398-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338A-B05398-GM FAQ
1.How can I place an order for SI5338A-B05398-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338A-B05398-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338A-B05398-GM reliable?
The price and inventory of SI5338A-B05398-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B05398-GM is usually 5 days.
3.What payment methods are accepted for SI5338A-B05398-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B05398-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338A-B05398-GM?
SI5338A-B05398-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338A-B05398-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338A-B05398-GM?
For technical support, including SI5338A-B05398-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B05398-GM requirements.
6.How does Aetrix verify that SI5338A-B05398-GM is sourced from the original manufacturer or authorized distributors?
All SI5338A-B05398-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B05398-GM meets industry standards.
7.What is the process for return or replacement of SI5338A-B05398-GM?
All SI5338A-B05398-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B05398-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338A-B05398-GM part is unused and in its original packaging.
Return procedure for SI5338A-B05398-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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