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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B05398-GMR

Name: SI5338A-B05398-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B05398-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B05398-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B05398-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338A-B05398-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338A-B05398-GMR datasheet, SI5338A-B05398-GMR pinout, SI5338A-B05398-GMR application, or SI5338A-B05398-GMR equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338A-B05398-GMR implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider for reference conditioning, followed by four independent MultiSynth™ fractional-N synthesis blocks (M0–M3) each driving a configurable output stage. Each MultiSynth supports integer or fractional mode with <1 ppb frequency resolution and ±45 ns programmable phase offset in <20 ps steps.

It accepts multiple reference inputs - external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) - and delivers up to four differential outputs (LVPECL/LVDS/HCSL/CML) or eight single-ended outputs (CMOS/SSTL/HSTL), with independent supply per output bank (VDDO0–VDDO3) and loss-of-lock/loss-of-signal alarms.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements.
Output Frequency Range	0.16–710 MHz per channel; supports PCIe 100 MHz HCSL, 125 MHz GbE, 155.52 MHz OC-12, and 100/125/250 MHz Ethernet/FPGA clocks.
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz); enables flexible system-level clock tree sourcing.
Output Format Flexibility	LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL - each output independently selectable with dedicated VDDO supply (1.5/1.8/2.5/3.3 V).
Spread Spectrum	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate; reduces EMI without requiring board-level filtering changes.
Supply & Power	Core: 1.8/2.5/3.3 V (±10%), 45 mA typical; output buffers: 1.4–3.63 V per VDDO rail; supports mixed-voltage clock distribution.
Operating Temperature	–40 to +85 °C ambient; qualified for industrial and telecom line card environments with no derating required.

Pinout & Package

SI5338A-B05398-GMR is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad (RoHS-compliant, lead-free). Pin assignments follow the standard Si5338 24-QFN layout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref), IN5/IN6 (differential ref 2), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDD (core supply), VDDO0–VDDO3 (output buffer supplies), SCL/SDA/INTR (I²C interface), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input 1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled via register; supports PCIe/SONET/10GbE references.
IN3 / IN4	Single-ended reference input	CMOS/SSTL/HSTL-compatible; 5–350 MHz range; 1.8/2.5/3.3 V tolerant; used for low-cost crystal oscillator or FPGA feedback paths.
CLK0A / CLK0B	Differential output 0 pair	LVPECL/LVDS/HCSL/CML configurable; independent VDDO0 supply; supports 0.16–710 MHz; critical for primary PCIe or Ethernet clock domain.
CLK1A / CLK1B	Differential output 1 pair	Independent frequency/format/voltage control; enables dual-clock-domain systems (e.g., processor + FPGA) without external buffers.
SCL / SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports in-system programming and dynamic frequency adjustment during runtime.
INTR	Interrupt output	Open-drain status signal asserting loss-of-lock or loss-of-signal; enables real-time system fault monitoring without polling.

Key Features

Feature	Design Value
MultiSynth™ synthesis engine	Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs - eliminates need for multiple crystals or trimming components.
Glitchless frequency adjustment	1 ppm step size via PINC/FDEC pins or I²C; avoids clock interruptions during dynamic scaling in networking or compute platforms.
Programmable phase offset	±45 ns range in <20 ps increments per output; enables precise skew management for DDR memory interfaces or SerDes alignment.
External feedback mode	Supports zero-delay configuration for clock forwarding applications (e.g., backplane distribution), reducing cumulative jitter accumulation.
Configurable spread spectrum	Per-output SSC with user-defined depth (0.5–5.0%) and rate (33–63 kHz); meets FCC/CE Class B emissions limits without hardware redesign.

Applications

PCIe Gen 3/4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz HCSL clocks to PCIe Gen 3/4 switch ICs and attached endpoints in enterprise servers and AI accelerators. IC Role / Device Role / Timing Role: Primary clock generator delivering compliant common clock topology with sub-0.32 ps RMS jitter per PCIe Gen 4 spec. Use Value: Eliminates need for discrete PCIe clock buffers and multiple XO sources while maintaining full Gen 4 link training reliability.	Use Scenario: Generating 125 MHz GbE and 156.25 MHz 10GbE clocks for multi-port Ethernet switches with mixed-rate PHYs. IC Role / Device Role / Timing Role: Quad-output timing source supporting independent frequency domains for 1G/2.5G/10G ports with shared reference stability. Use Value: Reduces BOM count by replacing four separate oscillators; maintains <0.7 ps RMS jitter across all rates for low packet error rate.
Broadcast Video Timing	FPGA & Processor Clocking
Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz clocks to video encoders, decoders, and frame synchronizers. IC Role / Device Role / Timing Role: Precision any-frequency synthesizer generating exact broadcast frequencies from a single 25 MHz crystal reference. Use Value: Achieves <1 ppb accuracy and <0.7 ps RMS jitter required for genlock stability and artifact-free HD/4K video transport.	Use Scenario: Supplying core, DDR, and peripheral clocks (e.g., 100 MHz, 200 MHz, 300 MHz) to Xilinx Versal or Intel Agilex FPGAs and ARM-based SoCs. IC Role / Device Role / Timing Role: Configurable clock hub providing format-matched (LVDS/HCSL/CMOS), voltage-matched (1.8/2.5/3.3 V), and phase-aligned outputs. Use Value: Enables single-chip clock solution for heterogeneous SoC/FPGA subsystems, simplifying power sequencing and layout.

PCIe Gen 3/4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz HCSL clocks to PCIe Gen 3/4 switch ICs and attached endpoints in enterprise servers and AI accelerators.

IC Role / Device Role / Timing Role: Primary clock generator delivering compliant common clock topology with sub-0.32 ps RMS jitter per PCIe Gen 4 spec.

Use Value: Eliminates need for discrete PCIe clock buffers and multiple XO sources while maintaining full Gen 4 link training reliability.

Use Scenario: Generating 125 MHz GbE and 156.25 MHz 10GbE clocks for multi-port Ethernet switches with mixed-rate PHYs.

IC Role / Device Role / Timing Role: Quad-output timing source supporting independent frequency domains for 1G/2.5G/10G ports with shared reference stability.

Use Value: Reduces BOM count by replacing four separate oscillators; maintains <0.7 ps RMS jitter across all rates for low packet error rate.

Broadcast Video Timing

FPGA & Processor Clocking

Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz clocks to video encoders, decoders, and frame synchronizers.

IC Role / Device Role / Timing Role: Precision any-frequency synthesizer generating exact broadcast frequencies from a single 25 MHz crystal reference.

Use Value: Achieves <1 ppb accuracy and <0.7 ps RMS jitter required for genlock stability and artifact-free HD/4K video transport.

Use Scenario: Supplying core, DDR, and peripheral clocks (e.g., 100 MHz, 200 MHz, 300 MHz) to Xilinx Versal or Intel Agilex FPGAs and ARM-based SoCs.

IC Role / Device Role / Timing Role: Configurable clock hub providing format-matched (LVDS/HCSL/CMOS), voltage-matched (1.8/2.5/3.3 V), and phase-aligned outputs.

Use Value: Enables single-chip clock solution for heterogeneous SoC/FPGA subsystems, simplifying power sequencing and layout.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B05400-GMR	Same silicon die and pinout; factory-programmed with different default configuration (e.g., output formats, frequencies, spread-spectrum settings).	Pre-configured for telecom line cards with 155.52/622.08 MHz outputs; requires no initial I²C programming for those use cases.	Select when pre-programmed startup behavior matches target system timing requirements and reduces firmware initialization overhead.
LMK04832RHAT	Two PLLs (not four independent MultiSynths); higher power (120 mA core); supports JESD204B deterministic latency but lacks per-output voltage control.	Optimized for RF/data converter timing with ultra-low additive jitter (<0.1 ps); less flexible for multi-protocol, multi-voltage clock trees.	Select when deterministic delay and sub-0.1 ps additive jitter are mandatory, and system uses only one or two clock domains with identical voltage requirements.

Compared with SI5338A-B05398-GMR, Si5338A-B05400-GMR offers identical hardware performance with factory-tuned defaults for faster time-to-operation, while LMK04832RHAT trades output flexibility and voltage independence for superior jitter cleanliness in narrowband RF applications.

Availability

SI5338A-B05398-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE routing infrastructure, and broadcast video synchronization requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338A-B05398-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family was designed as a programmable, low-jitter clock generator platform for high-speed serial interfaces - specifically targeting PCIe, Ethernet, Fibre Channel, and broadcast video systems where multi-frequency, multi-format, and multi-voltage clock distribution is essential.

FAQ

What is the default configuration of SI5338A-B05398-GMR at power-up?

The SI5338A-B05398-GMR powers up with factory-programmed OTP settings that configure it as a quad-output clock generator using a 25 MHz crystal reference, delivering four LVDS outputs at 100 MHz, 125 MHz, 156.25 MHz, and 312.5 MHz. These defaults are stored in one-time-programmable memory and require no I²C initialization to begin operation - though full reconfiguration remains possible via the SCL/SDA interface. SI5338A-B05398-GMR retains this behavior across all operating conditions.

Does SI5338A-B05398-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338A-B05398-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typ/max) when configured with a PLL bandwidth of 2–4 MHz and CDR set to 10 MHz. This compliance is verified per PCI-SIG Base Specification 4.0 rev. 0.5 and measured using the Skyworks PCIe Clock Jitter Tool. SI5338A-B05398-GMR achieves this using its MultiSynth™ engine in integer mode with optimized loop filter settings.

Can SI5338A-B05398-GMR generate two outputs above 350 MHz simultaneously?

Yes, SI5338A-B05398-GMR can generate two unique frequencies above 350 MHz simultaneously - specifically Fvco/4 and Fvco/6 - as permitted by its VCO architecture. For example, it can deliver 473.33 MHz and 550 MHz concurrently on separate outputs. However, more than two >350 MHz outputs are not supported due to VCO harmonic constraints. SI5338A-B05398-GMR enforces this limitation in hardware and reports invalid configurations via I²C status registers.

How does the independent output voltage feature work on SI5338A-B05398-GMR?

SI5338A-B05398-GMR provides four dedicated output supply rails - VDDO0, VDDO1, VDDO2, and VDDO3 - each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. Each rail powers one differential output pair (CLK0A/B through CLK3A/B), allowing mixed-voltage clock distribution (e.g., 1.8 V LVDS to an FPGA and 3.3 V CMOS to a microcontroller) without level shifters. SI5338A-B05398-GMR monitors each VDDO rail and asserts INTR on undervoltage detection.

Is ClockBuilder Pro software required to program SI5338A-B05398-GMR?

No, ClockBuilder Pro is optional but strongly recommended for SI5338A-B05398-GMR configuration. The device supports full I²C register-level programming per its 256-page register map, enabling custom firmware integration. However, ClockBuilder Pro automates MultiSynth™ parameter calculation, validates jitter/performance margins, generates initialization code (C/Python), and verifies PCIe/Ethernet compliance - significantly reducing development time. SI5338A-B05398-GMR operates with or without it, but ClockBuilder Pro ensures optimal configuration for demanding applications.

SI5338A-B05398-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B05398-GMR FAQ

1.How can I place an order for SI5338A-B05398-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B05398-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B05398-GMR reliable?

The price and inventory of SI5338A-B05398-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B05398-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B05398-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B05398-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B05398-GMR?

SI5338A-B05398-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B05398-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B05398-GMR?

For technical support, including SI5338A-B05398-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B05398-GMR requirements.

6.How does Aetrix verify that SI5338A-B05398-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B05398-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B05398-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B05398-GMR?

All SI5338A-B05398-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B05398-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B05398-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B05398-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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