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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B05494-GMR

Name: SI5338A-B05494-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B05494-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B05494-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B05494-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338A-B05494-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338A-B05494-GMR datasheet, SI5338A-B05494-GMR pinout, SI5338A-B05494-GMR application, or SI5338A-B05494-GMR equivalent, key selection criteria include its MultiSynth™ fractional-N synthesis architecture, independent per-output voltage (1.5/1.8/2.5/3.3 V), 1 ppm frequency increment/decrement capability, <20 ps phase step resolution, and 24-pin 4×4 mm QFN package with integrated loss-of-lock and loss-of-signal alarms.

Technical Context

The SI5338A-B05494-GMR implements a two-stage PLL architecture: a high-stability reference stage (with programmable R-divider) feeding a wideband VCO, followed by four independent MultiSynth™ fractional-N synthesis blocks (M0–M3) each driving one output pair. Each MultiSynth supports integer or fractional division with 1 ppb frequency resolution and programmable initial phase offset (±45 ns).

Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references. Output drivers are fully independent-supporting mixed signal formats, per-output supply voltages (VDDO0–VDDO3), spread-spectrum modulation (0.5–5.0% at 33–63 kHz), and glitchless frequency/phase adjustment via pin control or I²C.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 Common Clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 and Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Formats	LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL - all independently selectable per driver
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: 1.5/1.8/2.5/3.3 V (VDDO0–VDDO3)
Frequency Resolution	1 ppb (via MultiSynth™ fractional-N synthesis); true zero-ppm accuracy on all outputs
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture-sensitive level 3

Pinout & Package

SI5338A-B05494-GMR is housed in a 24-pin, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: pins 1–24 include six input clocks (IN1–IN6), four differential output pairs (CLK0A/B through CLK3A/B), four independent VDDO supplies (VDDO0–VDDO3), core VDD (pins 9–10), I²C interface (SCL/SDA), interrupt (INTR), and reserved ground (RSVD_GND).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential reference input	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3, IN4	Single-ended reference input	Supports 5–200 MHz CMOS-level clock; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A, CLK0B	Differential output pair 0	Configurable format (LVPECL/LVDS/HCSL/etc.); driven by MultiSynth M0
VDDO0	Output buffer supply 0	Independent 1.5/1.8/2.5/3.3 V supply for CLK0A/B; sets output swing and common-mode voltage
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt output	Open-drain status flag indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling any-frequency generation (0.16–710 MHz) with 1 ppb resolution and zero ppm error
PCIe Gen 1–4 compliance	Fully compliant with PCIe Gen 1/2/3 Common Clock and Gen 3 SRNS; validated for Gen 4 Common Clock jitter (≤0.45 ps RMS)
Per-output voltage control	Four independent VDDO supplies (VDDO0–VDDO3) allow mixed-voltage system interfacing without level shifters
Glitchless frequency tuning	Pin-controlled frequency increment/decrement in 1 ppm steps with ≤667 ns update time for outputs >18 MHz
Programmable phase alignment	Independent ±45 ns initial phase offset and <20 ps step resolution per output for precise skew management
Spread-spectrum capability	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, enabling EMI reduction without changing layout

Applications

PCIe Root Complex Timing	Ethernet Switch Clocking
Use Scenario: Generating synchronized 100 MHz reference clocks for multiple PCIe endpoints and switches in enterprise server backplanes. IC Role / Device Role / Timing Role: Quad-output clock generator providing four independent, low-jitter PCIe-compliant clocks with matched phase alignment. Use Value: Eliminates four discrete oscillators; enables single-point jitter control and dynamic frequency margining via I²C during system validation.	Use Scenario: Delivering 125 MHz, 156.25 MHz, and 312.5 MHz clocks to 1G/10G Ethernet PHYs and switch fabric ASICs in telecom aggregation switches. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer supporting mixed-rate Ethernet interfaces with independent output formatting (LVDS for PHYs, HCSL for SerDes). Use Value: Reduces BOM count and board area; avoids custom crystal sourcing by synthesizing exact IEEE 802.3 frequencies from a single 25 MHz crystal.
FPGA/ASIC Clock Tree	Broadcast Video Synchronization
Use Scenario: Providing multiple clock domains (e.g., 200 MHz logic, 400 MHz DDR, 1 GHz transceiver reference) to Xilinx Versal or Intel Agilex FPGAs. IC Role / Device Role / Timing Role: Programmable quad clock generator with independent voltage and format per output, directly interfacing with FPGA I/O banks. Use Value: Enables full clock tree integration on one IC; eliminates interposer-level clock distribution complexity and associated jitter accumulation.	Use Scenario: Generating SMPTE ST 2059-2 PTP-synchronized 27 MHz, 74.25 MHz, and 148.5 MHz video clocks for broadcast-grade SDI encoders/decoders and IP media gateways. IC Role / Device Role / Timing Role: Low-phase-jitter clock synthesizer with sub-20 ps phase step resolution for frame-accurate genlock and lip-sync alignment. Use Value: Meets SMPTE ST 2059-2 Class A timing stability; supports real-time phase adjustment to compensate for network delay variations in IP-based video workflows.

PCIe Root Complex Timing

Ethernet Switch Clocking

Use Scenario: Generating synchronized 100 MHz reference clocks for multiple PCIe endpoints and switches in enterprise server backplanes.

IC Role / Device Role / Timing Role: Quad-output clock generator providing four independent, low-jitter PCIe-compliant clocks with matched phase alignment.

Use Value: Eliminates four discrete oscillators; enables single-point jitter control and dynamic frequency margining via I²C during system validation.

Use Scenario: Delivering 125 MHz, 156.25 MHz, and 312.5 MHz clocks to 1G/10G Ethernet PHYs and switch fabric ASICs in telecom aggregation switches.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer supporting mixed-rate Ethernet interfaces with independent output formatting (LVDS for PHYs, HCSL for SerDes).

Use Value: Reduces BOM count and board area; avoids custom crystal sourcing by synthesizing exact IEEE 802.3 frequencies from a single 25 MHz crystal.

FPGA/ASIC Clock Tree

Broadcast Video Synchronization

Use Scenario: Providing multiple clock domains (e.g., 200 MHz logic, 400 MHz DDR, 1 GHz transceiver reference) to Xilinx Versal or Intel Agilex FPGAs.

IC Role / Device Role / Timing Role: Programmable quad clock generator with independent voltage and format per output, directly interfacing with FPGA I/O banks.

Use Value: Enables full clock tree integration on one IC; eliminates interposer-level clock distribution complexity and associated jitter accumulation.

Use Scenario: Generating SMPTE ST 2059-2 PTP-synchronized 27 MHz, 74.25 MHz, and 148.5 MHz video clocks for broadcast-grade SDI encoders/decoders and IP media gateways.

IC Role / Device Role / Timing Role: Low-phase-jitter clock synthesizer with sub-20 ps phase step resolution for frame-accurate genlock and lip-sync alignment.

Use Value: Meets SMPTE ST 2059-2 Class A timing stability; supports real-time phase adjustment to compensate for network delay variations in IP-based video workflows.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B05501-GM	Same Si5338A die; factory-programmed for fixed 100/125/156.25/312.5 MHz outputs; no I²C required	Targeted at cost-sensitive, high-volume PCIe/10GbE systems where configuration flexibility is unnecessary	Select when preconfigured outputs match design needs and I²C infrastructure is unavailable or undesired
LMK04832ISQE/NOPB	Two PLLs + eight outputs; higher power (120 mA); supports JESD204B deterministic latency; no spread spectrum	Preferred for JESD204B-compliant RF data converters requiring ultra-low deterministic jitter and multi-device synchronization	Select when deterministic latency, dual-loop redundancy, or >4 outputs are required-accept higher power and larger 48-QFN footprint

Compared with SI5338A-B05494-GMR, Si5338A-B05501-GM trades programmability for lower system cost and boot-time simplicity, while LMK04832ISQE/NOPB adds deterministic latency control and dual-PLL robustness at the expense of power, size, and lack of spread-spectrum EMI reduction.

Availability

SI5338A-B05494-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 root complexes, 10 GbE switch fabric timing, and FPGA-based broadcast video synchronizers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338A-B05494-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family is engineered for high-performance, multi-protocol clock generation in datacenter, networking, and broadcast equipment-delivering ultra-low jitter, flexible frequency synthesis, and seamless integration into complex timing architectures.

FAQ

What is the default configuration of SI5338A-B05494-GMR at power-up?

The SI5338A-B05494-GMR powers up with factory-programmed nonvolatile memory (OTP) settings that configure it as a fully functional quad clock generator. Default outputs are disabled until enabled via I²C or pin strapping; the device enters a known state with PLLs unlocked and all outputs in tri-state. Configuration persistence relies on OTP storage, not external EEPROM, ensuring reliable boot behavior without host intervention. SI5338A-B05494-GMR retains its last programmed state across power cycles unless explicitly reset or reprogrammed.

Does SI5338A-B05494-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338A-B05494-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical), meeting the PCI-SIG specification when configured with a PLL bandwidth of 2–4 MHz and CDR set to 10 MHz. This mode requires disabling spread-spectrum modulation and selecting appropriate loop filter components per Skyworks AN562. SI5338A-B05494-GMR achieves this using its dedicated MultiSynth™ synthesis stage and low-noise VCO architecture-validated with the Skyworks PCIe Clock Jitter Tool.

Can SI5338A-B05494-GMR generate three different frequencies above 350 MHz simultaneously?

No, SI5338A-B05494-GMR cannot generate three unique frequencies above 350 MHz simultaneously. Its architecture permits only two distinct outputs >350 MHz at once-specifically Fvco/4 and Fvco/6-as defined in the synthesis stage limitations. Attempting a third >350 MHz output will result in invalid frequency combinations or failure to lock. SI5338A-B05494-GMR supports up to four outputs total, but frequencies above 350 MHz are constrained to those two VCO-derived values per device instance.

How does the independent VDDO supply affect output signal integrity on SI5338A-B05494-GMR?

Each VDDO supply (VDDO0–VDDO3) directly sets the output driver's common-mode voltage and swing amplitude-for example, LVDS at 2.5 V VDDO yields 0.35 VPP single-ended swing, while 1.8 V VDDO yields 0.35 VPP with 0.875 V common mode. This allows SI5338A-B05494-GMR to drive mixed-voltage receivers (e.g., 1.8 V FPGA banks and 2.5 V PHYs) without external level shifters. Incorrect VDDO selection causes signal integrity degradation: undershoot/overshoot, duty cycle distortion, or failure to meet receiver thresholds.

Is ClockBuilder Pro software required to configure SI5338A-B05494-GMR in production?

No, ClockBuilder Pro is optional for development and evaluation; SI5338A-B05494-GMR can be fully configured in production via direct I²C register writes using customer firmware. ClockBuilder Pro generates register maps and configuration files (e.g., .c files) that may be embedded into bootloader code. SI5338A-B05494-GMR operates from factory OTP defaults and supports runtime reprogramming-enabling field updates, margin testing, or dynamic frequency scaling without tool dependency.

SI5338A-B05494-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B05494-GMR FAQ

1.How can I place an order for SI5338A-B05494-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B05494-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B05494-GMR reliable?

The price and inventory of SI5338A-B05494-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B05494-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B05494-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B05494-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B05494-GMR?

SI5338A-B05494-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B05494-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B05494-GMR?

For technical support, including SI5338A-B05494-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B05494-GMR requirements.

6.How does Aetrix verify that SI5338A-B05494-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B05494-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B05494-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B05494-GMR?

All SI5338A-B05494-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B05494-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B05494-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B05494-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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