Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B05495-GM

Name: SI5338A-B05495-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B05495-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338A-B05495-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B05495-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,240

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338A-B05495-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ) across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, supporting PCIe Gen 1–4 and Ethernet timing in telecom line cards and FPGA clocking.

For engineers reviewing the SI5338A-B05495-GM datasheet, SI5338A-B05495-GM pinout, SI5338A-B05495-GM application, or SI5338A-B05495-GM equivalent, this page provides verified technical context, exact pin functions, PCIe Gen 4 SRNS-compliant jitter performance, output voltage configurability per driver, and real-world use cases in broadcast video timing and 10 GbE systems.

Technical Context

The SI5338A-B05495-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each with programmable R/M/N dividers enabling any-frequency synthesis from 0.16 MHz to 710 MHz. It supports external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential inputs (5–710 MHz).

Each of its four differential output drivers is independently configurable for signal format, supply voltage (1.5/1.8/2.5/3.3 V), phase offset (<20 ps step), spread spectrum (0.5–5.0% at 33–63 kHz), and glitchless frequency increment/decrement in 1 ppm steps - all via I²C/SMBus interface with OTP NVM storage.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 Common Clock and Gen 3 SRNS requirements.
Output Frequency Range	0.16–710 MHz per channel; supports up to two outputs >350 MHz simultaneously (Fvco/4 & Fvco/6).
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver.
Package & Pins	24-pin QFN (4 × 4 mm); 4 differential clock outputs (CLK0A/B–CLK3A/B), 6 input pins (IN1–IN6), I²C (SCL/SDA), INTR, OEB.
Operating Temperature	–40 °C to +85 °C; qualified for industrial and telecom infrastructure applications.
Power Consumption	45 mA typical core current (100 MHz on all outputs, 25 MHz refclk); <12 mA in buffer mode.

Pinout & Package

SI5338A-B05495-GM uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	LVPECL/LVDS/HCSL/CML-compatible; independently configured format, voltage, and frequency.
CLK1A / CLK1B	Differential Output Pair 1	Same configurability as CLK0; supports integer/fractional synthesis with <20 ps phase step resolution.
CLK2A / CLK2B	Differential Output Pair 2	Glitchless frequency increment/decrement enabled via PINC/FDEC pins; zero-ppm accuracy.
CLK3A / CLK3B	Differential Output Pair 3	Supports spread spectrum (0.5–5.0% modulation depth, 33–63 kHz rate) for EMI reduction.
IN1 / IN2, IN5 / IN6	Differential Input Pairs	Accept 5–710 MHz differential clocks; require external 100 Ω termination for optimal jitter.
IN3 / IN4	Single-Ended Input Pins	Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD.
SCL / SDA	I²C Interface	Standard SMBus-compatible serial interface (up to 400 kHz); used with ClockBuilder Pro for configuration.
INTR	Interrupt Output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) events.
OEB	Output Enable Bar	Active-low global enable for all clock outputs; supports power sequencing and dynamic control.
VDD, VDDO0–VDDO3	Power Supplies	VDD = core supply (1.8/2.5/3.3 V); VDDOx = independent output buffer supplies (1.5–3.3 V).
GND, RSVD_GND	Ground Terminals	Multiple ground pins including reserved ground for noise isolation and thermal management.

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent fractional-N synthesizers deliver true zero-ppm precision across 0.16–710 MHz without external crystals.
PCIe Gen 4 Common Clock Compliance	0.15–0.45 ps RMS jitter (10 kHz–50 MHz) meets PCIe Base Spec 4.0 rev. 0.5 for common clock topology.
Per-Output Voltage & Format Configurability	Each of four outputs supports independent selection of LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL and 1.5/1.8/2.5/3.3 V supply.
Glitchless Frequency Tuning	1 ppm-step frequency increment/decrement via dedicated pins (PINC/FDEC) or I²C, with <667 ns update time.
Programmable Spread Spectrum	Configurable SSC on any output: 0.5–5.0% deviation, 33–63 kHz modulation rate, reducing EMI in dense PCB layouts.
External Feedback Zero-Delay Mode	Supports zero-delay operation using external feedback path, critical for deterministic latency in timing-critical systems.

Applications

Broadcast Video/Audio Timing	PCIe Gen 1–4 Clocking
Use Scenario: Synchronizing multi-channel HD/4K video encoders, audio sample-rate converters, and genlock distribution in broadcast studios. IC Role / Device Role / Timing Role: Quad-output clock generator providing frame-locked 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz clocks with sub-20 ps inter-output skew. Use Value: Eliminates multiple discrete oscillators; enables precise phase alignment across video/audio domains with <0.7 ps RMS jitter.	Use Scenario: Providing reference clocks to CPU, GPU, NVMe SSDs, and switch ICs in servers and workstations with PCIe Gen 4 interfaces. IC Role / Device Role / Timing Role: Common-clock source meeting PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS) across four slots or devices. Use Value: Reduces BOM count and layout complexity while maintaining Gen 4 compliance without requiring separate jitter cleaners.
FPGA & Processor Clocking	10 GbE Line Cards
Use Scenario: Delivering multiple domain-specific clocks (e.g., 100 MHz system, 250 MHz transceiver, 300 MHz DDR, 500 MHz logic) to Xilinx/Intel FPGAs and SoCs. IC Role / Device Role / Timing Role: Programmable quad clock generator with independent voltage and format per output, supporting mixed-voltage FPGA banks. Use Value: Enables single-chip clock tree for heterogeneous FPGA designs, reducing board area and power vs. discrete buffers and synthesizers.	Use Scenario: Generating synchronized 156.25 MHz, 312.5 MHz, and 625 MHz clocks for 10GBASE-R PHYs, MACs, and SerDes in telecom line cards. IC Role / Device Role / Timing Role: Low-jitter clock source compliant with IEEE 802.3ae and ITU-T G.8262 for synchronous Ethernet (SyncE) applications. Use Value: Meets stringent OC-12 (0.7 ps RMS) and 10GbE jitter specs while supporting flexible frequency translation between client and line rates.

Broadcast Video/Audio Timing

PCIe Gen 1–4 Clocking

Use Scenario: Synchronizing multi-channel HD/4K video encoders, audio sample-rate converters, and genlock distribution in broadcast studios.

IC Role / Device Role / Timing Role: Quad-output clock generator providing frame-locked 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz clocks with sub-20 ps inter-output skew.

Use Value: Eliminates multiple discrete oscillators; enables precise phase alignment across video/audio domains with <0.7 ps RMS jitter.

Use Scenario: Providing reference clocks to CPU, GPU, NVMe SSDs, and switch ICs in servers and workstations with PCIe Gen 4 interfaces.

IC Role / Device Role / Timing Role: Common-clock source meeting PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS) across four slots or devices.

Use Value: Reduces BOM count and layout complexity while maintaining Gen 4 compliance without requiring separate jitter cleaners.

FPGA & Processor Clocking

10 GbE Line Cards

Use Scenario: Delivering multiple domain-specific clocks (e.g., 100 MHz system, 250 MHz transceiver, 300 MHz DDR, 500 MHz logic) to Xilinx/Intel FPGAs and SoCs.

IC Role / Device Role / Timing Role: Programmable quad clock generator with independent voltage and format per output, supporting mixed-voltage FPGA banks.

Use Value: Enables single-chip clock tree for heterogeneous FPGA designs, reducing board area and power vs. discrete buffers and synthesizers.

Use Scenario: Generating synchronized 156.25 MHz, 312.5 MHz, and 625 MHz clocks for 10GBASE-R PHYs, MACs, and SerDes in telecom line cards.

IC Role / Device Role / Timing Role: Low-jitter clock source compliant with IEEE 802.3ae and ITU-T G.8262 for synchronous Ethernet (SyncE) applications.

Use Value: Meets stringent OC-12 (0.7 ps RMS) and 10GbE jitter specs while supporting flexible frequency translation between client and line rates.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05495-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated LDOs, smaller 32-QFN (4 × 4 mm).	Targets higher-density systems requiring >4 clocks or tighter jitter budgets (e.g., 5G baseband, AI accelerators).	Select when needing ≥8 outputs, sub-0.4 ps jitter, or simplified power delivery - not drop-in compatible due to pinout and register map changes.
ICS8430I-01T	Fixed-frequency quad LVDS generator (no I²C programming); 0.9 ps RMS jitter; 3.3 V only; 32-TQFP package.	Used in cost-sensitive, static-clocking applications where frequency flexibility is unnecessary (e.g., legacy storage controllers).	Choose only for non-programmable, fixed-frequency deployments; lacks MultiSynth™, spread spectrum, or voltage flexibility.

Compared with Si5332A-D05495-GM and ICS8430I-01T, the SI5338A-B05495-GM uniquely balances full I²C programmability, PCIe Gen 4 compliance, per-output voltage/format control, and proven field deployment in telecom and broadcast - making it optimal for mid-complexity, field-upgradable timing systems.

Availability

SI5338A-B05495-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, 10 GbE line cards, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338A-B05495-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5338A-B05495-GM belongs to Skyworks' Si5338 family of programmable clock generators, designed specifically for high-reliability, multi-protocol timing in datacenter, telecom, and broadcast systems demanding low jitter and field reconfigurability.

FAQ

What is the primary function of the SI5338A-B05495-GM in a system?

The SI5338A-B05495-GM serves as a quad-output, I²C-programmable clock generator that replaces up to four discrete oscillators. It synthesizes any frequency from 0.16 MHz to 710 MHz on each output with 0 ppm precision using MultiSynth™ technology, supporting PCIe Gen 4, 10 GbE, and broadcast video timing. Its role is to provide low-jitter, independently configurable clocks to FPGAs, processors, and SerDes blocks.

Does the SI5338A-B05495-GM support PCIe Gen 4 timing requirements?

Yes, the SI5338A-B05495-GM meets PCIe Gen 4 Common Clock jitter specifications: 0.15–0.45 ps RMS (10 kHz–50 MHz) and complies with PCIe Gen 3 Separate Reference No Spread (SRNS) requirements (0.11–0.32 ps RMS). These values are measured per Skyworks' datasheet Table 12 under specified conditions using HCSL 100 MHz outputs and Intel Clock Jitter Tool v1.6.4.

Can the SI5338A-B05495-GM generate different output voltages on each channel?

Yes, the SI5338A-B05495-GM supports independent output buffer supply voltages (VDDO0–VDDO3) selectable per channel at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows direct interfacing with mixed-voltage FPGA I/O banks or ASICs without level-shifting components - confirmed in datasheet Table 1 and functional description section 3.4.

How is the SI5338A-B05495-GM programmed and configured?

The SI5338A-B05495-GM is programmed via its I²C/SMBus-compatible serial interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration includes output frequencies, formats, voltages, spread spectrum settings, and phase offsets. Final settings are stored in one-time-programmable (OTP) NVM, enabling autonomous startup without host intervention.

What package type and thermal characteristics does the SI5338A-B05495-GM have?

The SI5338A-B05495-GM uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, enabling reliable operation from –40 °C to +85 °C ambient. Power dissipation is ≤250 mW at full load (45 mA core current @ 3.3 V).

SI5338A-B05495-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B05495-GM FAQ

1.How can I place an order for SI5338A-B05495-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B05495-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B05495-GM reliable?

The price and inventory of SI5338A-B05495-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B05495-GM is usually 5 days.

3.What payment methods are accepted for SI5338A-B05495-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B05495-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B05495-GM?

SI5338A-B05495-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B05495-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B05495-GM?

For technical support, including SI5338A-B05495-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B05495-GM requirements.

6.How does Aetrix verify that SI5338A-B05495-GM is sourced from the original manufacturer or authorized distributors?

All SI5338A-B05495-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B05495-GM meets industry standards.

7.What is the process for return or replacement of SI5338A-B05495-GM?

All SI5338A-B05495-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B05495-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B05495-GM part is unused and in its original packaging.

Return procedure for SI5338A-B05495-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…