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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B05696-GM

Name: SI5338A-B05696-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B05696-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B05696-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B05696-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338A-B05696-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338A-B05696-GM datasheet, SI5338A-B05696-GM pinout, SI5338A-B05696-GM application, or SI5338A-B05696-GM equivalent, key selection criteria include its MultiSynth™ fractional-N synthesis architecture, independent output voltage per driver (1.5/1.8/2.5/3.3 V), 0 ppm frequency accuracy on all outputs, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats up to 710 MHz.

Technical Context

The SI5338A-B05696-GM implements a two-stage PLL architecture: a reference-stage PLL locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks-each driving one output pair (CLKxA/CLKxB). Each MultiSynth supports integer or fractional mode with <1 ppb frequency resolution and programmable initial phase offset (±45 ns).

It features I²C/SMBus configuration, loss-of-lock and loss-of-signal alarms, independent output enable (OEB), glitchless frequency increment/decrement in 1 ppm steps, and spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation) on any output. The device operates from a single 1.8/2.5/3.3 V core supply and supports per-output buffer supplies from 1.4 V to 3.63 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V (1.4–3.63 V range)
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3
Operating Temperature	–40 °C to +85 °C ambient; qualified per industrial temperature grade
Power Consumption	45 mA typical core current at 100 MHz on all outputs with 25 MHz reference

Pinout & Package

SI5338A-B05696-GM is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair 1	Accepts AC-coupled differential reference (5–710 MHz); internal 100 Ω termination enabled
IN3, IN4	Single-ended input pair	Supports CMOS/SSTL/HSTL inputs (5–350 MHz); each pin configurable as separate input or complementary pair
IN5, IN6	Differential input pair 2	Second AC-coupled differential reference path; enables dual-reference redundancy or frequency switching
CLK0A, CLK0B	Differential output pair 0	LVPECL/LVDS/HCSL/CML configurable; independent voltage (VDDO0), enable (OEB), and phase control
CLK1A, CLK1B	Differential output pair 1	Same configurability as CLK0; supports independent format, frequency, and voltage vs. other outputs
CLK2A, CLK2B	Differential output pair 2	Independent MultiSynth™ stage; full frequency/format/voltage/phase control
CLK3A, CLK3B	Differential output pair 3	Fourth fully independent output; supports spread-spectrum, phase adjustment, and SSC modulation
SCL, SDA	I²C interface	Standard SMBus-compatible 2-wire serial interface for configuration and status readback
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock, loss-of-signal, or register-access error
VDD, VDDO0–VDDO3	Power supplies	VDD = core supply; VDDOx = dedicated output buffer supply per channel (1.4–3.63 V)
GND, RSVD_GND	Ground connections	Multiple GND pins including reserved ground for noise isolation; requires solid thermal pad connection

Key Features

Feature	Design Value
MultiSynth™ synthesis per output	Four independent fractional-N synthesizers enabling true any-frequency generation with 0 ppm accuracy on all outputs
PCIe Gen 1–4 compliance	Fully compliant with PCIe Gen 1/2/3 Common Clock and Gen 3 Separate Reference No Spread (SRNS) jitter specs
Glitchless frequency tuning	Independent 1 ppm-step frequency increment/decrement via pin or I²C without output interruption
Per-output voltage and format	Each output supports independent selection of LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL and 1.5/1.8/2.5/3.3 V drive
Programmable phase alignment	±45 ns initial phase offset and <20 ps step resolution for precise inter-channel skew control
Spread-spectrum clocking (SSC)	Configurable on any output: 0.5–5.0% spread depth, 33–63 kHz modulation rate, down-spread default

Applications

PCIe Root Complex Timing	FPGA/ASIC Clock Tree Synthesis
Use Scenario: Generating synchronized 100 MHz REFCLK and 125 MHz user clocks for multi-lane PCIe 4.0 endpoint with SRNS compliance. IC Role / Device Role / Timing Role: Quad-output clock generator providing PCIe-compliant reference and auxiliary clocks with deterministic phase relationships. Use Value: Eliminates need for four discrete oscillators; achieves 0.15 ps RMS jitter (Gen 4 spec) using internal MultiSynth™ synthesis and low-noise PLL architecture.	Use Scenario: Driving heterogeneous clock domains in Xilinx Versal ACAP-200 MHz logic, 300 MHz transceiver, 100 MHz DDR, and 50 MHz management clocks. IC Role / Device Role / Timing Role: Programmable frequency translator and buffer delivering four independent, format-matched clocks from a single 25 MHz crystal. Use Value: Reduces BOM count and PCB area; enables dynamic reconfiguration of clock frequencies via I²C during system boot or runtime.
Ethernet Switch Line Card	Broadcast Video Synchronization
Use Scenario: Providing 156.25 MHz SerDes clocks and 25 MHz management clocks for 10GbE/25GbE switch ASICs with jitter below 0.7 ps RMS. IC Role / Device Role / Timing Role: Low-jitter clock source meeting IEEE 802.3bj/802.3by jitter requirements for backplane and optical interfaces. Use Value: Delivers sub-1 ps RMS jitter across all outputs using differential LVDS drivers and optimized loop bandwidth (1.6 MHz typical).	Use Scenario: Generating SMPTE ST 2059-2 compliant 10 MHz, 27 MHz, and 74.25 MHz video reference clocks with <±50 ns phase alignment across outputs. IC Role / Device Role / Timing Role: Precision timing generator synchronizing camera, encoder, and display subsystems in broadcast infrastructure. Use Value: Achieves <20 ps phase step resolution and <100 ps output-to-output skew for frame-accurate genlock and lip-sync.

PCIe Root Complex Timing

FPGA/ASIC Clock Tree Synthesis

Use Scenario: Generating synchronized 100 MHz REFCLK and 125 MHz user clocks for multi-lane PCIe 4.0 endpoint with SRNS compliance.

IC Role / Device Role / Timing Role: Quad-output clock generator providing PCIe-compliant reference and auxiliary clocks with deterministic phase relationships.

Use Value: Eliminates need for four discrete oscillators; achieves 0.15 ps RMS jitter (Gen 4 spec) using internal MultiSynth™ synthesis and low-noise PLL architecture.

Use Scenario: Driving heterogeneous clock domains in Xilinx Versal ACAP-200 MHz logic, 300 MHz transceiver, 100 MHz DDR, and 50 MHz management clocks.

IC Role / Device Role / Timing Role: Programmable frequency translator and buffer delivering four independent, format-matched clocks from a single 25 MHz crystal.

Use Value: Reduces BOM count and PCB area; enables dynamic reconfiguration of clock frequencies via I²C during system boot or runtime.

Ethernet Switch Line Card

Broadcast Video Synchronization

Use Scenario: Providing 156.25 MHz SerDes clocks and 25 MHz management clocks for 10GbE/25GbE switch ASICs with jitter below 0.7 ps RMS.

IC Role / Device Role / Timing Role: Low-jitter clock source meeting IEEE 802.3bj/802.3by jitter requirements for backplane and optical interfaces.

Use Value: Delivers sub-1 ps RMS jitter across all outputs using differential LVDS drivers and optimized loop bandwidth (1.6 MHz typical).

Use Scenario: Generating SMPTE ST 2059-2 compliant 10 MHz, 27 MHz, and 74.25 MHz video reference clocks with <±50 ns phase alignment across outputs.

IC Role / Device Role / Timing Role: Precision timing generator synchronizing camera, encoder, and display subsystems in broadcast infrastructure.

Use Value: Achieves <20 ps phase step resolution and <100 ps output-to-output skew for frame-accurate genlock and lip-sync.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05689-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated crystal option; larger 32-QFN package	Required for systems needing >4 outputs or sub-0.5 ps jitter (e.g., 400G Ethernet, coherent optics)	Select when scaling beyond 4 clocks or requiring tighter jitter; not drop-in due to pinout and register map differences
ICS853S01I-01LF	Fixed-function 4-output LVDS generator; no I²C programming; 1.2 ps RMS jitter; 3.3 V only; 32-TQFP package	Suitable only for static, single-frequency designs (e.g., legacy telecom line cards with fixed 125/156.25 MHz)	Choose for cost-sensitive, non-reconfigurable applications where programmability is unnecessary

Compared with Si5332A-D05689-GM, SI5338A-B05696-GM offers smaller footprint and lower power but fewer outputs and higher jitter; versus ICS853S01I-01LF, it provides full field reprogrammability and multi-voltage support at the cost of higher design complexity.

Availability

SI5338A-B05696-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, FPGA clock tree synthesis, and broadcast video synchronization requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338A-B05696-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-where precise frequency synthesis and phase control are critical.

FAQ

What is the primary function of the SI5338A-B05696-GM in a system?

The SI5338A-B05696-GM serves as an I²C-programmable quad clock generator that synthesizes up to four independent, any-frequency output clocks from a single reference input. Its core function is to replace multiple discrete oscillators while delivering PCIe Gen 1–4–compliant jitter performance, making it ideal for FPGA, ASIC, and high-speed serial interface timing. SI5338A-B05696-GM integrates MultiSynth™ fractional-N synthesis, per-output voltage/format control, and spread-spectrum capability in a compact 4 × 4 mm QFN.

Does the SI5338A-B05696-GM support PCIe Gen 4 timing requirements?

Yes, the SI5338A-B05696-GM meets PCIe Gen 4 common clock jitter specifications with 0.15–0.45 ps RMS (10 kHz–50 MHz) under defined test conditions (100 MHz HCSL outputs, PLL BW 2–5 MHz, CDR = 10 MHz). It is explicitly listed in Skyworks documentation as PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliant. SI5338A-B05696-GM achieves this via its low-noise PLL architecture, optimized loop bandwidth, and differential output drivers.

Can the SI5338A-B05696-GM generate different output voltages simultaneously?

Yes, the SI5338A-B05696-GM supports independent output buffer supply voltages per channel: VDDO0 through VDDO3 can each be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V (within 1.4–3.63 V range). This allows simultaneous LVPECL (3.3 V), LVDS (2.5 V), HCSL (1.8 V), and CMOS (1.5 V) outputs without external level-shifting. SI5338A-B05696-GM uses dedicated VDDO pins and internal regulators to maintain signal integrity across mixed-voltage configurations.

What reference inputs does the SI5338A-B05696-GM accept?

The SI5338A-B05696-GM accepts six reference input types: (1) 8–30 MHz fundamental-mode crystal on IN1/IN2; (2) CMOS single-ended (5–200 MHz) on IN3 or IN4; (3) SSTL/HSTL (5–350 MHz) on IN3/IN4; (4) differential (5–710 MHz) on IN1/IN2; (5) differential on IN5/IN6; and (6) external clock on IN3/IN4 configured as complementary pair. SI5338A-B05696-GM auto-detects input type and configures termination accordingly.

How is the SI5338A-B05696-GM programmed and configured?

The SI5338A-B05696-GM is configured via its I²C/SMBus-compatible 2-wire serial interface (SCL/SDA pins), supporting standard 100 kHz and 400 kHz modes. Configuration is simplified using Skyworks' ClockBuilder Pro software, which generates custom configuration files and registers settings based on user-defined frequencies, formats, and features. SI5338A-B05696-GM also supports pin-controlled frequency increment/decrement and hardware reset for field updates without host processor intervention.

SI5338A-B05696-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B05696-GM FAQ

1.How can I place an order for SI5338A-B05696-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B05696-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B05696-GM reliable?

The price and inventory of SI5338A-B05696-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B05696-GM is usually 5 days.

3.What payment methods are accepted for SI5338A-B05696-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B05696-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B05696-GM?

SI5338A-B05696-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B05696-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B05696-GM?

For technical support, including SI5338A-B05696-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B05696-GM requirements.

6.How does Aetrix verify that SI5338A-B05696-GM is sourced from the original manufacturer or authorized distributors?

All SI5338A-B05696-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B05696-GM meets industry standards.

7.What is the process for return or replacement of SI5338A-B05696-GM?

All SI5338A-B05696-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B05696-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B05696-GM part is unused and in its original packaging.

Return procedure for SI5338A-B05696-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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