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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B05808-GM

Name: SI5338A-B05808-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B05808-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B05808-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B05808-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338A-B05808-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.

For engineers reviewing the SI5338A-B05808-GM datasheet, SI5338A-B05808-GM pinout, SI5338A-B05808-GM application, or SI5338A-B05808-GM equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe/PCIe Gen 4 timing compliance, real-world output format flexibility (LVPECL/LVDS/HCSL/CMOS), and two technically documented alternative parts for frequency synthesis applications.

Technical Context

The SI5338A-B05808-GM implements a dual-stage PLL architecture: a high-stability reference stage (Synthesis Stage 1) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating precise output frequencies from 0.16 MHz to 710 MHz. Each output supports programmable voltage (1.5/1.8/2.5/3.3 V), phase offset (±45 ns), and spread-spectrum modulation (0.5–5.0% at 33–63 kHz).

It features loss-of-lock and loss-of-signal alarms, independent frequency increment/decrement (1 ppm steps), and glitchless reconfiguration via I²C or hardware pins. The device operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw and integrates OTP NVM for factory or field programming.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements for high-speed serial links.
Output Frequency Range	0.16–710 MHz - supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz).
Input Flexibility	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables reuse of legacy timing sources.
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V - simplifies mixed-voltage system integration.
Package	24-pin QFN, 4 × 4 mm - space-efficient footprint compatible with high-density PCB layouts and automated assembly.
Temperature Range	–40 to +85 °C - qualified for industrial and telecom line card environments without derating.
I²C Interface	SMBus-compatible, 100/400 kHz - enables host MCU-based dynamic reconfiguration without external programmers.

Pinout & Package

SI5338A-B05808-GM uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.6 datasheet (pages 33–37) and functional block diagram.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair	Accepts 5–710 MHz AC-coupled differential clocks; requires external 100 Ω termination.
IN3, IN4	Single-ended input pair	Supports 5–200 MHz CMOS-level inputs; VIH = 0.7×VDD, VIL = 0.3×VDD.
CLK0A, CLK0B – CLK3A, CLK3B	Differential output pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each with programmable VDDOx (1.5–3.3 V).
VDDO0–VDDO3	Output buffer supplies	Separate power rails per output bank enable mixed-signal interface voltage translation.
VDD	Core supply	Single 1.8/2.5/3.3 V rail powers PLL, logic, and NVM; PSRR optimized for noisy environments.
SCL, SDA	I²C control interface	Standard bidirectional bus; supports multi-device addressing and register-level configuration.
INTR	Interrupt output	Open-drain status flag for loss-of-lock or loss-of-signal events; pulls low on alarm condition.
RSVD_GND	Reserved ground	Internal test pin; must be connected to GND per layout guidelines (page 40).

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers deliver true zero-ppm accuracy on all outputs without external VCXOs.
PCIe Gen 4 compliance	0.15–0.45 ps RMS jitter in common clock mode meets PCIe Base Spec 4.0 rev. 0.5 requirements for 16 GT/s links.
Independent phase adjustment	±45 ns range in <20 ps steps enables precise skew alignment across multi-lane SerDes interfaces.
Spread spectrum support	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output reduces EMI in dense board layouts.
External feedback mode	Enables zero-delay operation for clock forwarding applications without added propagation latency.
Glitchless frequency tuning	Hardware pin-controlled 1 ppm increment/decrement allows real-time clock rate adaptation during system operation.

Applications

Ethernet Switch/Routing	PCIe Gen 1–4 Interconnect
Use Scenario: High-port-count 1/10 GbE switches requiring synchronized packet timing and low-jitter reference clocks for PHYs and MACs. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 125 MHz, 156.25 MHz, and 312.5 MHz clocks to multiple PHY lanes and management controllers. Use Value: Eliminates four discrete oscillators while maintaining sub-1 ps RMS jitter required for IEEE 802.3bj KR4 compliance.	Use Scenario: Server motherboard with CPU, GPU, and NVMe SSDs sharing a common PCIe reference clock tree. IC Role / Device Role / Timing Role: PCIe Gen 4-compliant common clock source delivering 100 MHz HCSL to root complex and endpoints with SRNS validation. Use Value: Meets Intel Clock Jitter Tool v1.6.4 pass criteria (0.15–0.45 ps RMS) without external jitter cleaners.
Broadcast Video/Audio Timing	FPGA & Processor Clocking
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing platform requiring ultra-low-jitter 74.25 MHz and 148.5 MHz pixel clocks. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact SMPTE-aligned frequencies from a single 27 MHz crystal reference. Use Value: Achieves 0.7 ps RMS jitter-well below SMPTE RP 184-2017 1.5 ps RMS limit for broadcast-grade timing.	Use Scenario: Xilinx Kintex Ultrascale+ FPGA design needing separate clocks for transceivers (161.1328125 MHz), DDR4 memory (1200 MHz DDR), and AXI interconnect (100 MHz). IC Role / Device Role / Timing Role: Configurable quad clock generator supplying LVDS, HCSL, and CMOS outputs simultaneously from one IC. Use Value: Reduces BOM count and layout complexity versus discrete clock buffers and synthesizers.

Ethernet Switch/Routing

PCIe Gen 1–4 Interconnect

Use Scenario: High-port-count 1/10 GbE switches requiring synchronized packet timing and low-jitter reference clocks for PHYs and MACs.

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 125 MHz, 156.25 MHz, and 312.5 MHz clocks to multiple PHY lanes and management controllers.

Use Value: Eliminates four discrete oscillators while maintaining sub-1 ps RMS jitter required for IEEE 802.3bj KR4 compliance.

Use Scenario: Server motherboard with CPU, GPU, and NVMe SSDs sharing a common PCIe reference clock tree.

IC Role / Device Role / Timing Role: PCIe Gen 4-compliant common clock source delivering 100 MHz HCSL to root complex and endpoints with SRNS validation.

Use Value: Meets Intel Clock Jitter Tool v1.6.4 pass criteria (0.15–0.45 ps RMS) without external jitter cleaners.

Broadcast Video/Audio Timing

FPGA & Processor Clocking

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing platform requiring ultra-low-jitter 74.25 MHz and 148.5 MHz pixel clocks.

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact SMPTE-aligned frequencies from a single 27 MHz crystal reference.

Use Value: Achieves 0.7 ps RMS jitter-well below SMPTE RP 184-2017 1.5 ps RMS limit for broadcast-grade timing.

Use Scenario: Xilinx Kintex Ultrascale+ FPGA design needing separate clocks for transceivers (161.1328125 MHz), DDR4 memory (1200 MHz DDR), and AXI interconnect (100 MHz).

IC Role / Device Role / Timing Role: Configurable quad clock generator supplying LVDS, HCSL, and CMOS outputs simultaneously from one IC.

Use Value: Reduces BOM count and layout complexity versus discrete clock buffers and synthesizers.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generation applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05808-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated crystal option; larger 32-QFN package.	Targets next-gen PCIe Gen 5 and 200G Ethernet where tighter jitter and more outputs are required.	Select when >4 outputs or sub-0.5 ps RMS jitter is mandatory; not drop-in due to pin count and package size.
ICS8430I-01LG	Fixed-frequency, non-programmable quad LVDS clock fanout buffer; no synthesis capability; 0.9 ps RMS jitter.	Used only in static clock distribution scenarios with known, unchanging frequencies.	Choose only if no frequency agility is needed and cost sensitivity outweighs programmability benefits.

Compared with Si5332A-D05808-GM and ICS8430I-01LG, the SI5338A-B05808-GM uniquely balances field-programmable frequency synthesis, PCIe Gen 4 compliance, compact 24-QFN packaging, and proven deployment in volume telecom and datacom platforms-making it optimal for designs requiring adaptability without over-spec'ing.

Availability

SI5338A-B05808-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 interconnect, and FPGA clocking applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338A-B05808-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family was designed for high-performance, software-configurable clock generation in datacenter, telecom, and broadcast equipment-emphasizing low jitter, multi-format output flexibility, and robust I²C programmability.

FAQ

What is the maximum output frequency supported by SI5338A-B05808-GM in LVPECL mode?

The SI5338A-B05808-GM supports LVPECL outputs up to 710 MHz, as specified in Table 6 of the Skyworks datasheet Rev. 1.6. This applies when using differential outputs with proper termination and within the device's thermal limits (θJA = 37 °C/W). Frequencies above 350 MHz require Fvco/4 or Fvco/6 synthesis modes and are limited to two unique outputs simultaneously.

Does SI5338A-B05808-GM support PCIe Gen 4 Common Clock compliance?

Yes, SI5338A-B05808-GM is explicitly validated for PCIe Gen 4 Common Clock operation with 0.15–0.45 ps RMS jitter (Table 12), meeting PCI-SIG Base Specification 4.0 rev. 0.5 requirements. Testing used 100 MHz HCSL outputs and the Intel Clock Jitter Tool v1.6.4 per AN562 guidelines.

Can SI5338A-B05808-GM generate different output formats simultaneously?

Yes, SI5338A-B05808-GM supports simultaneous LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL outputs across its four differential pairs. Each CLKxA/CLKxB pair is independently configurable for signal format and output voltage (1.5/1.8/2.5/3.3 V), enabling direct interfacing with mixed-voltage ASICs, FPGAs, and PHYs.

What crystal frequency ranges are supported by SI5338A-B05808-GM?

SI5338A-B05808-GM supports external crystals from 8 to 30 MHz, segmented into four validated bands: 8–11 MHz, 11–19 MHz, 19–26 MHz, and 26–30 MHz (Tables 8–11). Load capacitance support is 11–13 pF (on-chip), with 17–19 pF recommended for optimal stability and ESR ≤300 Ω.

Is ClockBuilder Pro software required to configure SI5338A-B05808-GM?

No, ClockBuilder Pro is optional but strongly recommended for SI5338A-B05808-GM configuration. The device can be programmed directly via I²C using custom firmware; however, ClockBuilder Pro provides validated GUI-based setup, jitter optimization, register export, and PCIe/SDI compliance checks unavailable in raw register writes.

SI5338A-B05808-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B05808-GM FAQ

1.How can I place an order for SI5338A-B05808-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B05808-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B05808-GM reliable?

The price and inventory of SI5338A-B05808-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B05808-GM is usually 5 days.

3.What payment methods are accepted for SI5338A-B05808-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B05808-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B05808-GM?

SI5338A-B05808-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B05808-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B05808-GM?

For technical support, including SI5338A-B05808-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B05808-GM requirements.

6.How does Aetrix verify that SI5338A-B05808-GM is sourced from the original manufacturer or authorized distributors?

All SI5338A-B05808-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B05808-GM meets industry standards.

7.What is the process for return or replacement of SI5338A-B05808-GM?

All SI5338A-B05808-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B05808-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B05808-GM part is unused and in its original packaging.

Return procedure for SI5338A-B05808-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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