Skyworks Solutions Inc. SI5338A-B05859-GM
- Part No.:
- SI5338A-B05859-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338A-B05859-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:1,889
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338A-B05859-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in FPGA/processor clocking, PCIe timing, and broadcast video systems.
For engineers reviewing the SI5338A-B05859-GM datasheet, SI5338A-B05859-GM pinout, SI5338A-B05859-GM application, or SI5338A-B05859-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro software integration.
Technical Context
The SI5338A-B05859-GM implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis paths, each feeding a configurable output driver. This enables true zero-ppm frequency accuracy on all outputs without shared dividers or frequency coupling.
Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent supply rails (VDDO0–VDDO3), programmable phase offset (<20 ps step resolution), and glitchless frequency increment/decrement in 1 ppm steps. Input flexibility includes differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and crystal (8–30 MHz) references.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and GbE jitter requirements |
| Output Frequency Range | 0.16–710 MHz per channel; supports integer/fractional synthesis with <1 ppb resolution |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Output Format Flexibility | LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL per channel; independent VDDO (1.5/1.8/2.5/3.3 V) |
| Spread Spectrum | Configurable down-spread (0.5–5.0%) at 33–63 kHz modulation rate on any output |
| Supply & Temp Range | Core: 1.8/2.5/3.3 V ±10%; operating ambient: –40 to +85 °C; 45 mA typical core current |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, lead-free |
Pinout & Package
SI5338A-B05859-GM uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, with dedicated differential inputs (IN1/IN2, IN5/IN6), single-ended inputs (IN3/IN4), four differential output pairs (CLK0A/B through CLK3A/B), I²C interface (SCL/SDA), interrupt (INTR), and independent output supply pins (VDDO0–VDDO3).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1/IN2, IN5/IN6 | Differential clock inputs | Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination |
| IN3/IN4 | Single-ended clock inputs | Support 5–200 MHz CMOS/SSTL/HSTL; DC-coupled with internal bias |
| CLK0A/CLK0B – CLK3A/CLK3B | Differential output pairs | Four independent outputs; each configurable for LVPECL/LVDS/HCSL/CML with dedicated VDDO |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5/1.8/2.5/3.3 V rails per output pair; enable mixed-voltage system interfacing |
| SCL/SDA | I²C/SMBus interface | Standard 100/400 kHz operation; supports ClockBuilder Pro programming and runtime reconfiguration |
| INTR | Interrupt output | Open-drain status signal indicating loss-of-lock or loss-of-signal events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Any-Frequency Synthesis | Four independent output channels, each synthesizing any frequency from 0.16 to 710 MHz with 0 ppm error in integer mode |
| PCIe Gen 1–4 Timing Compliance | Meets Common Clock (Gen 1/2/3/4) and Gen 3 SRNS jitter specs (≤0.32 ps RMS) without external filtering |
| Programmable Phase Offset | ±45 ns range with <20 ps step resolution per output; enables precise skew control in multi-clock domain systems |
| Glitchless Frequency Adjustment | 1 ppm step size via PINC/FDEC pins or I²C; no output interruption during dynamic frequency changes |
| Flexible Spread Spectrum | Per-output down-spread (0.5–5.0%) at user-selectable 33–63 kHz rates; reduces EMI in dense PCB layouts |
| Zero-Delay Mode Support | External feedback path enables synchronous clock distribution with minimal propagation delay variation |
Applications
| PCIe Gen 3/4 Root Complex | Ethernet Switch Timing |
|---|---|
Use Scenario: Providing synchronized reference clocks to CPU, GPU, and peripheral controllers in server/mainboard designs with PCIe Gen 3/4 lanes. IC Role / Device Role / Timing Role: Quad-output clock generator delivering 100 MHz common clock and 125 MHz SerDes reference with SRNS-compliant jitter. Use Value: Eliminates need for multiple discrete oscillators; ensures PCIe link stability and compliance with ≤0.32 ps RMS jitter requirement. |
Use Scenario: Generating independent clocks for 1 GbE and 10 GbE PHYs, packet buffers, and switch fabric in enterprise Ethernet switches. IC Role / Device Role / Timing Role: Configurable clock source supporting LVDS (125 MHz), HCSL (156.25 MHz), and CMOS (25 MHz) outputs simultaneously. Use Value: Enables single-chip timing for multi-rate Ethernet subsystems while maintaining <1 ps RMS jitter on critical SerDes links. |
| Broadcast Video Synchronization | FPGA-Based Video Processing |
Use Scenario: Distributing frame-locked timing signals (e.g., 27 MHz, 74.25 MHz, 148.5 MHz) across SDI transceivers, video encoders, and genlock circuits. IC Role / Device Role / Timing Role: Precision clock synthesizer generating SMPTE-compliant frequencies with sub-20 ps phase step resolution. Use Value: Ensures pixel-accurate synchronization across multi-channel video pipelines without external PLLs or delay lines. |
Use Scenario: Supplying configurable clocks to Xilinx/Kintex or Intel/Arria FPGA banks requiring different I/O standards (LVDS, SSTL, HSTL) and frequencies. IC Role / Device Role / Timing Role: Programmable clock generator delivering 100 MHz LVDS, 300 MHz HSTL, and 50 MHz CMOS from one device. Use Value: Reduces BOM count and layout complexity while enabling dynamic reconfiguration of FPGA clock domains via I²C. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05859-GM | Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated EEPROM, supports JESD204B deterministic latency | Targeted at high-speed data converters and 5G wireless infrastructure where sub-0.4 ps jitter and deterministic delay are mandatory | Select when >4 outputs, ultra-low jitter, or JESD204B timing alignment are required; higher cost and larger 32-QFN package |
| ICS843002AGI-01LFT | Fixed-function 4-output LVDS generator; no I²C programmability; 1.2 ps RMS jitter; 100–700 MHz range | Used in cost-sensitive, high-volume applications where frequency flexibility is not needed (e.g., fixed-rate video interfaces) | Select only for static clock trees with known, unchanging frequencies; lacks Si5338A-B05859-GM's any-frequency synthesis and voltage/format flexibility |
Compared with Si5332A-D05859-GM and ICS843002AGI-01LFT, the SI5338A-B05859-GM uniquely balances field-programmability, PCIe Gen 4 readiness, and compact 24-QFN packaging-making it optimal for mid-complexity embedded systems requiring design reuse across multiple clock configurations without hardware respins.
Availability
SI5338A-B05859-GM is available at Aetrix Electronics and suitable for PCIe timing, Ethernet switch/router development, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338A-B05859-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for communications, automotive, and industrial markets.
The SI5338A-B05859-GM belongs to Skyworks' Si5338 family of programmable clock generators, designed specifically for high-performance, multi-protocol timing in compute, networking, and media infrastructure where flexible, low-jitter clock synthesis replaces discrete oscillator arrays.
FAQ
What is the maximum output frequency supported by the SI5338A-B05859-GM?
The SI5338A-B05859-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS outputs. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) per Skyworks Rev. 1.6 datasheet Section 3.3.
Does the SI5338A-B05859-GM support PCIe Gen 4 Common Clock compliance?
Yes, the SI5338A-B05859-GM meets PCIe Gen 4 Common Clock jitter specifications (≤0.45 ps RMS, 10 kHz–50 MHz) per Table 12 of the Skyworks datasheet, verified using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4 with 100 MHz HCSL outputs.
Can the SI5338A-B05859-GM generate different output voltages on each channel?
Yes - the SI5338A-B05859-GM provides independent VDDO0–VDDO3 supply pins, allowing each of its four output pairs to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V simultaneously. This enables direct interfacing with mixed-voltage FPGA I/O banks or ASIC clock inputs without level shifters.
How is the SI5338A-B05859-GM programmed, and is external nonvolatile memory required?
The SI5338A-B05859-GM is programmed via I²C/SMBus interface using Skyworks' ClockBuilder Pro software. It contains on-chip OTP NVM that stores configuration; no external EEPROM is required for factory-programmed startup behavior. Runtime reprogramming is fully supported.
What input reference options does the SI5338A-B05859-GM support?
The SI5338A-B05859-GM accepts eight input reference types: 8–30 MHz crystal (differential), 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential (LVDS/LVPECL/CML). All inputs support automatic loss-of-signal detection with configurable timeout thresholds.
SI5338A-B05859-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338A-B05859-GM FAQ
1.How can I place an order for SI5338A-B05859-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338A-B05859-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338A-B05859-GM reliable?
The price and inventory of SI5338A-B05859-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B05859-GM is usually 5 days.
3.What payment methods are accepted for SI5338A-B05859-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B05859-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338A-B05859-GM?
SI5338A-B05859-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338A-B05859-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338A-B05859-GM?
For technical support, including SI5338A-B05859-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B05859-GM requirements.
6.How does Aetrix verify that SI5338A-B05859-GM is sourced from the original manufacturer or authorized distributors?
All SI5338A-B05859-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B05859-GM meets industry standards.
7.What is the process for return or replacement of SI5338A-B05859-GM?
All SI5338A-B05859-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B05859-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338A-B05859-GM part is unused and in its original packaging.
Return procedure for SI5338A-B05859-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338A-B05859-GM Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

