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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B05859-GMR

Name: SI5338A-B05859-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B05859-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B05859-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B05859-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338A-B05859-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency differential or single-ended clocks (up to 710 MHz LVPECL/LVDS), 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces multiple crystal oscillators in FPGA, processor, and Ethernet switch timing systems.

For engineers reviewing the SI5338A-B05859-GMR datasheet, SI5338A-B05859-GMR pinout, SI5338A-B05859-GMR application, or SI5338A-B05859-GMR equivalent, key selection criteria include its 4-output flexibility, sub-1 ps RMS jitter performance, PCIe Gen 4-compliant common-clock operation, independent output voltage per driver (1.5–3.3 V), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338A-B05859-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) feeding a fractional-N VCO, followed by four independent MultiSynth™ synthesis blocks. Each output path includes configurable dividers, format-selectable drivers (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), and per-output voltage control.

It supports flexible reference inputs - 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential - and enables glitchless frequency adjustment in 1 ppm steps and phase tuning in <20 ps increments. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring via the INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count	4 independent outputs with configurable format, frequency, and voltage per driver
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common-clock jitter spec
Max Output Frequency	710 MHz (LVPECL/LVDS), 350 MHz (SSTL/HSTL), 250 MHz (HCSL), 200 MHz (CMOS)
Input Reference Range	8–30 MHz crystal; 5–710 MHz differential; 5–350 MHz SSTL/HSTL; 5–200 MHz CMOS
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5–3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temp	–40 °C to +85 °C ambient; suitable for industrial and telecom line-card environments

Pinout & Package

SI5338A-B05859-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are standardized across the Si5338 family and validated per Skyworks Rev. 1.6 datasheet (pages 33–37).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support 5–200 MHz CMOS-level clocks; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each pair configurable per format and voltage
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz interface for configuration; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status pin indicating loss-of-lock or loss-of-signal events
VDD	Core supply	1.8/2.5/3.3 V ±10% core power; PSRR optimized for low-noise clock generation
GND, RSVD_GND	Ground terminals	Multiple GND pins including reserved ground for noise isolation and thermal management

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm frequency accuracy on all four outputs without external crystals
PCIe Gen 4 Common Clock compliance	0.15–0.45 ps RMS jitter (10 kHz–50 MHz) meets PCIe Base Spec 4.0 rev. 0.5 requirements
Independent output voltage per driver	Each of four output banks supports 1.5/1.8/2.5/3.3 V, enabling direct interface to mixed-voltage FPGAs and ASICs
Glitchless frequency adjustment	1 ppm step size with hardware pin control (FINC/FDEC) or I²C; no output interruption during tuning
Programmable spread spectrum	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output to reduce EMI in dense PCB layouts
External feedback mode	Supports zero-delay operation for clock distribution networks requiring precise phase alignment

Applications

Ethernet Switch Timing	PCIe Gen 4 Server Clocking
Use Scenario: High-density 10/25/100 GbE switch fabric requiring synchronized clocks across multiple SerDes lanes and packet processors. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 312.5 MHz (CAUI), 100 MHz (control plane), and 250 MHz (PHY interface) clocks with matched skew and sub-1 ps jitter. Use Value: Eliminates four discrete oscillators; reduces board area and BOM count while meeting IEEE 802.3bj jitter masks for 100GBASE-KR4.	Use Scenario: Dual-CPU server motherboard with PCIe Gen 4 x16 slots, NVMe storage controllers, and platform controller hub (PCH). IC Role / Device Role / Timing Role: Common-clock source delivering 100 MHz PCIe refclk to CPU, PCH, and add-in cards with Gen 4 SRNS compliance and <0.32 ps RMS jitter. Use Value: Ensures PCIe link training success and long-term reliability under thermal stress; avoids costly re-spin due to jitter-related link failures.
Broadcast Video Synchronization	FPGA-Based Test Equipment
Use Scenario: SMPTE ST 2082 (12G-SDI) video router requiring frame-accurate genlock across 64+ channels with ultra-low jitter. IC Role / Device Role / Timing Role: Master clock synthesizer generating 27 MHz, 74.25 MHz, and 148.5 MHz outputs with <10 ps cycle-cycle jitter and programmable phase offset. Use Value: Enables deterministic video pipeline latency and eliminates frame tearing in multi-channel broadcast infrastructure.	Use Scenario: High-speed digital pattern generator using Xilinx UltraScale+ FPGA, requiring multiple precisely phased clocks for DDR4 memory, ADC sampling, and serial I/O. IC Role / Device Role / Timing Role: Configurable clock source delivering 300 MHz (DDR4), 500 MHz (ADC), 125 MHz (PCIe), and 100 MHz (system) with independent phase tuning per output. Use Value: Synchronizes time-critical signal acquisition paths; enables sub-nanosecond timing correlation between analog and digital domains.

Ethernet Switch Timing

PCIe Gen 4 Server Clocking

Use Scenario: High-density 10/25/100 GbE switch fabric requiring synchronized clocks across multiple SerDes lanes and packet processors.

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 312.5 MHz (CAUI), 100 MHz (control plane), and 250 MHz (PHY interface) clocks with matched skew and sub-1 ps jitter.

Use Value: Eliminates four discrete oscillators; reduces board area and BOM count while meeting IEEE 802.3bj jitter masks for 100GBASE-KR4.

Use Scenario: Dual-CPU server motherboard with PCIe Gen 4 x16 slots, NVMe storage controllers, and platform controller hub (PCH).

IC Role / Device Role / Timing Role: Common-clock source delivering 100 MHz PCIe refclk to CPU, PCH, and add-in cards with Gen 4 SRNS compliance and <0.32 ps RMS jitter.

Use Value: Ensures PCIe link training success and long-term reliability under thermal stress; avoids costly re-spin due to jitter-related link failures.

Broadcast Video Synchronization

FPGA-Based Test Equipment

Use Scenario: SMPTE ST 2082 (12G-SDI) video router requiring frame-accurate genlock across 64+ channels with ultra-low jitter.

IC Role / Device Role / Timing Role: Master clock synthesizer generating 27 MHz, 74.25 MHz, and 148.5 MHz outputs with <10 ps cycle-cycle jitter and programmable phase offset.

Use Value: Enables deterministic video pipeline latency and eliminates frame tearing in multi-channel broadcast infrastructure.

Use Scenario: High-speed digital pattern generator using Xilinx UltraScale+ FPGA, requiring multiple precisely phased clocks for DDR4 memory, ADC sampling, and serial I/O.

IC Role / Device Role / Timing Role: Configurable clock source delivering 300 MHz (DDR4), 500 MHz (ADC), 125 MHz (PCIe), and 100 MHz (system) with independent phase tuning per output.

Use Value: Synchronizes time-critical signal acquisition paths; enables sub-nanosecond timing correlation between analog and digital domains.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05859-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), but larger 32-QFN (5 × 5 mm) package	Targeted at next-gen 400G/800G optical modules and AI accelerators needing >4 outputs and tighter jitter budgets	Select when >4 outputs or <0.4 ps RMS jitter is required; avoid if board space or cost sensitivity favors 24-QFN footprint
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS clock buffer; no synthesis capability; 1.2 ps RMS jitter; 3.3 V only	Used in legacy systems where frequencies are static and design change is prohibited	Choose only for drop-in replacement in existing designs with unchanging clock trees; not suitable for any-frequency synthesis needs

Compared with SI5338A-B05859-GMR, Si5332A-D05859-GM offers higher channel count and lower jitter at increased cost and size, while ICS8430I-01T provides fixed-frequency buffering without programmability-making SI5338A-B05859-GMR the optimal balance of flexibility, jitter performance, and compact QFN packaging for new PCIe/Ethernet/FPGA designs.

Availability

SI5338A-B05859-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 1–4 server clocking, and broadcast video synchronization requiring stable component supply, full traceability, and long-term lifecycle support.

Supply support for SI5338A-B05859-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking innovation.

The Si5338 product line was designed for high-performance, multi-protocol timing in datacenter, telecom, and broadcast systems-enabling consolidation of discrete oscillators into a single, software-configurable IC with industry-leading jitter and flexibility.

FAQ

What is the primary function of the SI5338A-B05859-GMR in a system?

The SI5338A-B05859-GMR serves as a quad-output, any-frequency clock generator that synthesizes up to four independent, low-jitter clock signals from a single reference input. Its MultiSynth™ technology enables precise frequency generation (0 ppm error) for applications like PCIe, Ethernet, and FPGA clocking-replacing multiple discrete oscillators while maintaining tight phase alignment and jitter performance critical for high-speed serial links.

Does the SI5338A-B05859-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338A-B05859-GMR meets PCIe Gen 4 Common Clock specifications with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) when configured per Skyworks AN562 guidelines. It is explicitly validated for PCIe Gen 4 compliance in the Rev. 1.6 datasheet and supports both Common Clock and Gen 3 SRNS modes, making SI5338A-B05859-GMR suitable for server, storage, and accelerator platforms requiring Gen 4 link stability.

Can the SI5338A-B05859-GMR generate different output formats simultaneously?

Yes, the SI5338A-B05859-GMR supports simultaneous mixed-format outputs: for example, CLK0A/B as LVDS, CLK1A/B as HCSL, CLK2A/B as LVPECL, and CLK3A/B as CMOS-all independently configured. Each output bank (VDDO0–VDDO3) allows separate voltage selection (1.5–3.3 V) and format assignment, enabling direct interface to heterogeneous devices like FPGAs, ASICs, and SerDes PHYs within a single SI5338A-B05859-GMR instance.

How is the SI5338A-B05859-GMR programmed and configured?

The SI5338A-B05859-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which auto-generates register maps, validates configurations, and exports .c files for embedded initialization. Configuration can be stored in on-chip OTP NVM for power-on default operation. Hardware pin control (FINC/FDEC, OEB) also enables real-time frequency/phase adjustment without host intervention-ensuring SI5338A-B05859-GMR remains fully controllable in both development and field-deployed systems.

What thermal and power characteristics define the SI5338A-B05859-GMR's suitability for industrial use?

The SI5338A-B05859-GMR operates across –40 °C to +85 °C ambient, with 37 °C/W junction-to-ambient thermal resistance and 10 °C/W junction-to-case rating-enabling reliable operation in thermally constrained industrial and telecom line-card environments. Its typical core current draw is 45 mA at 100 MHz on all outputs, and output buffer currents scale with format/frequency (e.g., 30 mA max for LVPECL @ 710 MHz), ensuring predictable power delivery and thermal management for SI5338A-B05859-GMR in continuous-duty applications.

SI5338A-B05859-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B05859-GMR FAQ

1.How can I place an order for SI5338A-B05859-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B05859-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B05859-GMR reliable?

The price and inventory of SI5338A-B05859-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B05859-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B05859-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B05859-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B05859-GMR?

SI5338A-B05859-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B05859-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B05859-GMR?

For technical support, including SI5338A-B05859-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B05859-GMR requirements.

6.How does Aetrix verify that SI5338A-B05859-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B05859-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B05859-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B05859-GMR?

All SI5338A-B05859-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B05859-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B05859-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B05859-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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