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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B05923-GM

Name: SI5338A-B05923-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B05923-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B05923-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B05923-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338A-B05923-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, processor/FPGA clocking, and PCIe timing systems.

For engineers reviewing the SI5338A-B05923-GM datasheet, SI5338A-B05923-GM pinout, SI5338A-B05923-GM application, or SI5338A-B05923-GM equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe/PCIe Gen 4 timing compliance, real-world output format flexibility (LVPECL/LVDS/HCSL/CMOS), and accurate alternative part comparisons for clock tree design and BOM optimization.

Technical Context

The SI5338A-B05923-GM implements a dual-stage synthesis architecture: a PLL-based Stage 1 (with 1.6 MHz loop bandwidth) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ Stage 2 synthesizers per output. Each MultiSynth supports integer or fractional-N division with 1 ppb frequency resolution.

It features per-output voltage selection (1.5/1.8/2.5/3.3 V), independent phase adjustment (<20 ps steps), glitchless frequency increment/decrement (1 ppm steps), and programmable spread-spectrum on any output (0.5–5.0% spread, 33–63 kHz modulation). Loss-of-lock and loss-of-signal alarms are integrated with I²C/SMBus interface support.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements
Output Count & Flexibility	Four independent outputs: up to 4 differential (LVPECL/LVDS/HCSL/CML) or 8 single-ended (CMOS/SSTL/HSTL), or mixed configuration
Frequency Range	0.16–710 MHz per output; supports >350 MHz on two unique frequencies simultaneously (Fvco/4 and Fvco/6)
Input Reference Options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; output buffers: independently selectable 1.4–3.63 V per driver
Operating Temperature	–40 to +85 °C; qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture-sensitive level 3

Pinout & Package

SI5338A-B05923-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B to CLK3A/CLK3B	Differential output pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each configurable for format and voltage
VDDO0–VDDO3	Output buffer supply rails	Independent 1.4–3.63 V supplies per output pair; enable mixed-voltage clock distribution
VDD	Core supply	1.8/2.5/3.3 V ±10% core power; typical current draw 45 mA at 100 MHz on all outputs
SCL, SDA	I²C interface	SMBus-compatible serial control; supports standard/fast-mode (100/400 kHz)
INTR	Interrupt output	Open-drain status indicator for loss-of-lock or loss-of-signal events
RSVD_GND	Reserved ground	Internally connected to die substrate; must be tied to PCB ground plane

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent, any-frequency synthesizers with true zero-ppm accuracy and 1 ppb resolution
PCIe timing compliance	Fully compliant with PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS jitter specs (≤0.32 ps RMS)
Glitchless frequency tuning	Hardware-supported frequency increment/decrement in 1 ppm steps without output interruption
Per-output voltage control	Each output pair powered by dedicated VDDO rail (1.5/1.8/2.5/3.3 V), enabling multi-voltage SoC interfacing
Programmable spread spectrum	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, reducing EMI in dense PCB layouts
External feedback mode	Supports zero-delay operation for clock forwarding applications with precise input-to-output phase alignment

Applications

Ethernet Switch/Router Timing	PCIe Gen 4 Common Clock Distribution
Use Scenario: High-density 10 GbE/25 GbE switching fabric requiring low-jitter, multi-frequency clocking for MAC, PHY, and packet processor ICs. IC Role / Device Role / Timing Role: Quad clock generator providing synchronized 156.25 MHz, 312.5 MHz, and 625 MHz clocks with <0.45 ps RMS jitter to meet IEEE 802.3bj and PCIe Gen 4 spec. Use Value: Eliminates four discrete oscillators; reduces board area by 65% and enables dynamic frequency scaling via I²C during link training.	Use Scenario: Server motherboard with dual CPU sockets and multiple PCIe Gen 4 x16 slots needing a single, jitter-clean reference source. IC Role / Device Role / Timing Role: Common clock generator delivering four identical 100 MHz HCSL outputs meeting PCIe Gen 4 SRNS jitter limit (≤0.32 ps RMS). Use Value: Replaces legacy oscillator + fanout buffer solution; achieves 30% lower power (45 mA core) and eliminates inter-clock skew via internal MultiSynth synchronization.
Broadcast Video/Audio Synchronization	Processor and FPGA Clocking
Use Scenario: SMPTE ST 2082/ST 2110 IP video transport system requiring genlock-capable, low-phase-noise clocks for ADC/DAC, serializer/deserializer, and media processor blocks. IC Role / Device Role / Timing Role: Programmable clock source generating 74.25 MHz (HD), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) with <10 ps pk-pk period jitter. Use Value: Enables frame-accurate multi-channel sync via programmable initial phase offset (±45 ns) and hardware phase adjust (<20 ps steps).	Use Scenario: Heterogeneous compute platform integrating ARM Cortex-A72, Xilinx Zynq Ultrascale+, and high-speed ADCs requiring isolated, voltage-matched clocks. IC Role / Device Role / Timing Role: Configurable clock hub supplying 500 MHz LVDS to FPGA fabric, 1 GHz CMOS to processor core, and 122.88 MHz LVDS to ADC - all from one device. Use Value: Reduces BOM count by 4; avoids external level translators via per-output VDDO selection (1.8 V for FPGA, 3.3 V for legacy peripherals).

Ethernet Switch/Router Timing

PCIe Gen 4 Common Clock Distribution

Use Scenario: High-density 10 GbE/25 GbE switching fabric requiring low-jitter, multi-frequency clocking for MAC, PHY, and packet processor ICs.

IC Role / Device Role / Timing Role: Quad clock generator providing synchronized 156.25 MHz, 312.5 MHz, and 625 MHz clocks with <0.45 ps RMS jitter to meet IEEE 802.3bj and PCIe Gen 4 spec.

Use Value: Eliminates four discrete oscillators; reduces board area by 65% and enables dynamic frequency scaling via I²C during link training.

Use Scenario: Server motherboard with dual CPU sockets and multiple PCIe Gen 4 x16 slots needing a single, jitter-clean reference source.

IC Role / Device Role / Timing Role: Common clock generator delivering four identical 100 MHz HCSL outputs meeting PCIe Gen 4 SRNS jitter limit (≤0.32 ps RMS).

Use Value: Replaces legacy oscillator + fanout buffer solution; achieves 30% lower power (45 mA core) and eliminates inter-clock skew via internal MultiSynth synchronization.

Broadcast Video/Audio Synchronization

Processor and FPGA Clocking

Use Scenario: SMPTE ST 2082/ST 2110 IP video transport system requiring genlock-capable, low-phase-noise clocks for ADC/DAC, serializer/deserializer, and media processor blocks.

IC Role / Device Role / Timing Role: Programmable clock source generating 74.25 MHz (HD), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) with <10 ps pk-pk period jitter.

Use Value: Enables frame-accurate multi-channel sync via programmable initial phase offset (±45 ns) and hardware phase adjust (<20 ps steps).

Use Scenario: Heterogeneous compute platform integrating ARM Cortex-A72, Xilinx Zynq Ultrascale+, and high-speed ADCs requiring isolated, voltage-matched clocks.

IC Role / Device Role / Timing Role: Configurable clock hub supplying 500 MHz LVDS to FPGA fabric, 1 GHz CMOS to processor core, and 122.88 MHz LVDS to ADC - all from one device.

Use Value: Reduces BOM count by 4; avoids external level translators via per-output VDDO selection (1.8 V for FPGA, 3.3 V for legacy peripherals).

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06889-GM	Higher integration: 8 outputs, integrated EEPROM, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B SerDes, 5G wireless, and radar where sub-0.4 ps jitter and deterministic delay are mandatory	Select when migrating to higher channel count or requiring factory-programmed configurations and tighter jitter specs
ICS8430I-01T	Fixed-function 4-output LVDS fanout buffer; no frequency synthesis; 0.9 ps RMS jitter; no I²C interface	Used only in clock distribution (not generation); requires external master oscillator; limited to 700 MHz max output	Select only for simple fanout scenarios where frequency agility and multi-format support are unnecessary

Compared with SI5338A-B05923-GM, Si5332A-D06889-GM offers superior jitter and configurability but at higher cost and complexity, while ICS8430I-01T provides lower-cost distribution-only capability without synthesis or voltage flexibility - making SI5338A-B05923-GM the optimal balance of programmability, jitter performance, and multi-voltage support for PCIe/Ethernet/FPGA designs.

Availability

SI5338A-B05923-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 4 common clock distribution, and broadcast video/audio synchronization requiring stable component supply, long-term lifecycle assurance, and full traceability.

Supply support for SI5338A-B05923-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed specifically for high-performance, software-configurable clock generation in data center, telecom, and broadcast equipment - emphasizing low jitter, multi-output flexibility, and PCIe/SONET/Ethernet compliance.

FAQ

What is the primary function of the SI5338A-B05923-GM in a timing architecture?

The SI5338A-B05923-GM serves as an I²C-programmable quad clock generator that synthesizes up to four independent, any-frequency output clocks from a single input reference. Its core function is to replace multiple discrete oscillators or crystal-based clock sources while delivering ultra-low jitter (0.7 ps RMS), PCIe Gen 4 compliance, and flexible output formats - all within a compact 4 × 4 mm QFN package. This makes SI5338A-B05923-GM ideal for space-constrained, high-reliability timing applications.

Does the SI5338A-B05923-GM support PCIe Gen 4 timing requirements?

Yes, the SI5338A-B05923-GM meets PCIe Gen 4 common clock jitter specifications with ≤0.45 ps RMS (12 kHz–20 MHz) when configured per Skyworks' recommended settings - including 100 MHz HCSL outputs, PLL bandwidth of 2–4 MHz, and CDR = 10 MHz. It is explicitly validated for PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS modes per the official datasheet Table 12 and AN562 application note. SI5338A-B05923-GM does not require external components to achieve this compliance.

Can the SI5338A-B05923-GM generate different output voltages on its four clock channels?

Yes, the SI5338A-B05923-GM supports independent output buffer supply voltages: VDDO0 through VDDO3 can each be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous generation of LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) signals from a single SI5338A-B05923-GM device - eliminating level translators and simplifying multi-voltage SoC or FPGA clock tree design. Each VDDO rail powers its corresponding CLKxA/CLKxB pair.

How is the SI5338A-B05923-GM programmed, and what tools are required?

The SI5338A-B05923-GM is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software - a free, GUI-based tool that generates register maps, validates configurations, and exports .c files for embedded initialization. Programming can be performed in-system or pre-programmed at manufacturing. No external programmer hardware is needed beyond a standard I²C host controller. SI5338A-B05923-GM also supports pin-controlled frequency/phase adjustments (PINC/FDEC/OEB) for runtime tuning.

What is the maximum output frequency supported by the SI5338A-B05923-GM, and under what conditions?

The SI5338A-B05923-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs and 350 MHz on SSTL/HSTL outputs. However, only two unique frequencies above 350 MHz can be generated simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO architecture constraints. For full 710 MHz operation on all four outputs, the device must be configured in integer-mode synthesis with appropriate VCO calibration. These limits are specified in Table 6 of the Skyworks Si5338 datasheet Rev. 1.6.

SI5338A-B05923-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B05923-GM FAQ

1.How can I place an order for SI5338A-B05923-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B05923-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B05923-GM reliable?

The price and inventory of SI5338A-B05923-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B05923-GM is usually 5 days.

3.What payment methods are accepted for SI5338A-B05923-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B05923-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B05923-GM?

SI5338A-B05923-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B05923-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B05923-GM?

For technical support, including SI5338A-B05923-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B05923-GM requirements.

6.How does Aetrix verify that SI5338A-B05923-GM is sourced from the original manufacturer or authorized distributors?

All SI5338A-B05923-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B05923-GM meets industry standards.

7.What is the process for return or replacement of SI5338A-B05923-GM?

All SI5338A-B05923-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B05923-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B05923-GM part is unused and in its original packaging.

Return procedure for SI5338A-B05923-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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