Skyworks Solutions Inc. SI5338A-B06038-GM

Overview

SI5338A-B06038-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.

For engineers reviewing the SI5338A-B06038-GM datasheet, SI5338A-B06038-GM pinout, SI5338A-B06038-GM application, or SI5338A-B06038-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% spread), and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338A-B06038-GM implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its synthesis resolution is 1 ppb, enabling true zero-ppm frequency accuracy on all outputs.

It supports flexible input references - 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential - and offers independent phase adjustment (<20 ps steps), glitchless frequency increment/decrement (1 ppm steps), and loss-of-lock/loss-of-signal alarms for system monitoring.

Key Specifications

Pinout & Package

SI5338A-B06038-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), and pin numbering proceeds counterclockwise. The package supports standard reflow profiles per JEDEC J-STD-020 and provides low thermal resistance (θ_JA = 37 °C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338A-B06081-GM, the SI5338A-B06038-GM offers full field programmability via I²C rather than fixed factory configuration, enabling dynamic frequency updates; versus LMK04832RHAT, it delivers lower power and smaller footprint at the expense of dual-loop jitter cleaning capability.

Availability

SI5338A-B06038-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 infrastructure, and FPGA-based broadcast video timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338A-B06038-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 family is designed as a highly configurable, low-jitter clock generator targeting high-speed digital systems including PCIe, Ethernet, telecom, and FPGA platforms where precise, flexible, and compact timing is critical.

FAQ

What is the default factory configuration of the SI5338A-B06038-GM?

The SI5338A-B06038-GM ships with non-volatile memory (OTP) pre-programmed for a specific frequency set defined by Skyworks' B06038 variant code. Unlike blank parts, it powers up with valid clocks immediately but remains fully reprogrammable via I²C. Configuration details-including output frequencies, formats, and voltages-are documented in Skyworks Application Note AN981 and accessible through ClockBuilder Pro software.

Does the SI5338A-B06038-GM support PCIe Gen 4 Common Clock mode?

Yes, the SI5338A-B06038-GM meets PCIe Gen 4 Common Clock jitter requirements (0.15–0.45 ps RMS) when configured per Skyworks' AN562 guidelines, using a 2–4 MHz PLL bandwidth and 100 MHz HCSL outputs. Validation was performed with the Skyworks PCIe Clock Jitter Tool and Agilent 90804 oscilloscope per PCI-SIG specifications.

Can the SI5338A-B06038-GM generate four different frequencies above 350 MHz simultaneously?

No. Per Skyworks documentation (Section 3.3, Rev. 1.6), only two unique frequencies above 350 MHz can be generated simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints. Higher-frequency outputs must share one of those two synthesis paths, limiting concurrent >350 MHz outputs to two distinct values.

What is the maximum allowable load capacitance for the crystal connected to the SI5338A-B06038-GM?

The SI5338A-B06038-GM supports crystal load capacitances of 11–13 pF (on-chip differential tuning range), with 17–19 pF recommended for optimal stability. For crystals outside this range, register adjustments per AN360 are required. The part accepts 8–30 MHz fundamental-mode crystals with ESR ≤300 Ω and drive level ≤100 µW.

How does the SI5338A-B06038-GM handle loss-of-signal detection on its input clocks?

The SI5338A-B06038-GM provides configurable loss-of-signal (LOS) detection on all six input pins (IN1–IN6) with programmable thresholds. Detection time is 2.6–5 µs, and release time is 0.01–1 µs. LOS status is reported via the INTR pin and readable through I²C registers, enabling host firmware to trigger failover or alarm routines without external circuitry.