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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B06038-GMR

Name: SI5338A-B06038-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B06038-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B06038-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B06038-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338A-B06038-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338A-B06038-GMR datasheet, SI5338A-B06038-GMR pinout, SI5338A-B06038-GMR application, or SI5338A-B06038-GMR equivalent, key selection criteria include differential output jitter performance, I²C configurability of per-output voltage (1.5–3.3 V), spread-spectrum control, and PCIe Gen 4 common-clock compliance at 100 MHz HCSL.

Technical Context

The SI5338A-B06038-GMR integrates a fractional-N PLL with two-stage MultiSynth™ synthesis: first-stage PLL locks to an input reference (crystal, CMOS, or differential, 5–710 MHz), then four independent MultiSynth™ dividers generate precise output frequencies. Each output driver supports format and voltage configuration (1.5/1.8/2.5/3.3 V), phase adjustment (<20 ps steps), and glitchless frequency increment/decrement (1 ppm steps).

It features loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and programmable spread spectrum (0.5–5.0% spread, 33–63 kHz modulation). The device operates across –40 to +85 °C with core supply options of 1.8 V, 2.5 V, or 3.3 V and achieves <100 ps output-to-output skew under matched conditions.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 4 common-clock jitter requirement (≤0.45 ps RMS) when configured per spec
Output Frequency Range	0.16–710 MHz - supports PCIe 100 MHz, Ethernet 125/156.25 MHz, Fibre Channel 1.0625 GHz (via Fvco/4)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system clock sourcing
Output Formats	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - allows direct interfacing to FPGAs, processors, SerDes PHYs without level-shifting
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.5/1.8/2.5/3.3 V - supports mixed-voltage board designs with per-output rail independence
Package	24-pin QFN, 4 × 4 mm - compact footprint compatible with high-density PCB layouts and automated assembly
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line-card environments

Pinout & Package

SI5338A-B06038-GMR uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential Input Pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-Ended Inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL with internal biasing
CLK0A/CLK0B–CLK3A/CLK3B	Differential Output Pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each configurable for format and voltage
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.5/1.8/2.5/3.3 V rails per output bank - enables mixed-signal interface compatibility
SCL/SDA	I²C Interface	Standard SMBus-compatible 100/400 kHz interface for register programming and status readback
INTR	Interrupt Output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal events
VDD	Core Supply	Single 1.8/2.5/3.3 V supply powering PLL, synthesizers, and control logic
GND / RSVD_GND	Ground Terminals	Multiple GND pins and reserved ground pad ensure low-impedance return paths and EMI control

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Generates four independent outputs from 0.16 to 710 MHz with true zero-ppm accuracy - eliminates need for multiple crystals or fixed-ratio PLLs
PCIe Gen 4 Common Clock Compliance	Meets ≤0.45 ps RMS jitter requirement at 100 MHz HCSL output - validated per PCI-SIG Base Spec 4.0 rev 0.5
Per-Output Voltage & Format Control	Each of four output banks supports independent selection of 1.5/1.8/2.5/3.3 V supply and LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL - simplifies multi-protocol board design
Glitchless Frequency Adjustment	1 ppm step size with hardware pin control (PINC/FINC) - enables real-time dynamic frequency scaling without clock interruption
Programmable Spread Spectrum	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output - reduces EMI peak emissions in noise-sensitive systems
External Feedback Mode	Supports zero-delay clock distribution by feeding CLKOUT back as reference - maintains deterministic phase alignment across cascaded devices

Applications

Ethernet Switch Timing	PCIe Gen 4 Host Interface
Use Scenario: Synchronizing 10 GbE PHYs, MACs, and packet buffers in Layer 3 switches with strict jitter budgets. IC Role / Device Role / Timing Role: Quad-output clock generator providing 125 MHz (XAUI), 156.25 MHz (10GBase-R), and 312.5 MHz (PAM4) clocks with sub-1 ps RMS jitter. Use Value: Enables single-chip timing for multi-rate Ethernet interfaces while meeting IEEE 802.3bj jitter limits (≤1.2 ps RMS random jitter).	Use Scenario: Delivering synchronized 100 MHz reference clocks to CPU, GPU, and NVMe controllers in server motherboards. IC Role / Device Role / Timing Role: PCIe Gen 4 common-clock source with HCSL outputs meeting SRNS jitter spec (≤0.32 ps RMS) and CDR lock range. Use Value: Eliminates need for four discrete oscillators; ensures simultaneous clock delivery with <100 ps inter-output skew for coherent link training.
Broadcast Video Synchronization	FPGA-Based Signal Processing
Use Scenario: Generating frame-locked pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and audio word clocks (48/96 kHz) in SDI video encoders. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing SMPTE ST 2082-compliant timing with <±50 ns phase offset control. Use Value: Replaces crystal+divider chains; supports frame-accurate genlock via programmable initial phase offset (–45 to +45 ns).	Use Scenario: Providing multiple domain clocks (e.g., 200 MHz fabric, 300 MHz ADC interface, 125 MHz PCIe) to Xilinx Versal or Intel Agilex FPGAs. IC Role / Device Role / Timing Role: Configurable buffer and level translator with independent LVDS (200 MHz), HCSL (100 MHz), and CMOS (50 MHz) outputs. Use Value: Reduces BOM count and layout complexity; avoids external level shifters via per-output VDDO selection (1.8 V/2.5 V/3.3 V).

Ethernet Switch Timing

PCIe Gen 4 Host Interface

Use Scenario: Synchronizing 10 GbE PHYs, MACs, and packet buffers in Layer 3 switches with strict jitter budgets.

IC Role / Device Role / Timing Role: Quad-output clock generator providing 125 MHz (XAUI), 156.25 MHz (10GBase-R), and 312.5 MHz (PAM4) clocks with sub-1 ps RMS jitter.

Use Value: Enables single-chip timing for multi-rate Ethernet interfaces while meeting IEEE 802.3bj jitter limits (≤1.2 ps RMS random jitter).

Use Scenario: Delivering synchronized 100 MHz reference clocks to CPU, GPU, and NVMe controllers in server motherboards.

IC Role / Device Role / Timing Role: PCIe Gen 4 common-clock source with HCSL outputs meeting SRNS jitter spec (≤0.32 ps RMS) and CDR lock range.

Use Value: Eliminates need for four discrete oscillators; ensures simultaneous clock delivery with <100 ps inter-output skew for coherent link training.

Broadcast Video Synchronization

FPGA-Based Signal Processing

Use Scenario: Generating frame-locked pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and audio word clocks (48/96 kHz) in SDI video encoders.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing SMPTE ST 2082-compliant timing with <±50 ns phase offset control.

Use Value: Replaces crystal+divider chains; supports frame-accurate genlock via programmable initial phase offset (–45 to +45 ns).

Use Scenario: Providing multiple domain clocks (e.g., 200 MHz fabric, 300 MHz ADC interface, 125 MHz PCIe) to Xilinx Versal or Intel Agilex FPGAs.

IC Role / Device Role / Timing Role: Configurable buffer and level translator with independent LVDS (200 MHz), HCSL (100 MHz), and CMOS (50 MHz) outputs.

Use Value: Reduces BOM count and layout complexity; avoids external level shifters via per-output VDDO selection (1.8 V/2.5 V/3.3 V).

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06038-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs	Targeted at space-constrained, ultra-low-jitter applications (e.g., 5G baseband, optical transport); requires no external crystal	Select when crystal integration and sub-0.4 ps jitter are required; not drop-in due to different pinout and higher cost
ICS853S01AG-01T	Fixed-frequency, non-programmable; 4 LVDS outputs; 1.2 ps RMS jitter; 3.3 V only	Limited to static clock trees (e.g., legacy PCIe Gen 2, SATA); no I²C, no spread spectrum, no voltage flexibility	Select only for cost-sensitive, unchanging clock requirements where programmability is unnecessary

Compared with Si5332A-D06038-GM and ICS853S01AG-01T, SI5338A-B06038-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and per-output voltage/format control in a 4×4 mm QFN - making it optimal for reconfigurable, multi-standard platforms requiring post-silicon timing tuning.

Availability

SI5338A-B06038-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 host interface, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338A-B06038-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed to replace multiple fixed-frequency oscillators with a single, software-configurable clock generator for high-speed serial interfaces - targeting PCIe, Ethernet, Fibre Channel, and broadcast video timing systems.

FAQ

What is the primary function of the SI5338A-B06038-GMR in a timing architecture?

The SI5338A-B06038-GMR serves as a quad-output, I²C-programmable clock generator that synthesizes four independent, any-frequency clocks (0.16–710 MHz) from a single reference. Its MultiSynth™ technology enables zero-ppm precision and per-output format/voltage configuration - making SI5338A-B06038-GMR ideal for replacing multiple crystals in PCIe, Ethernet, and FPGA-based systems.

Does the SI5338A-B06038-GMR support PCIe Gen 4 common-clock timing requirements?

Yes, the SI5338A-B06038-GMR is explicitly validated for PCIe Gen 4 common-clock operation. When configured with 100 MHz HCSL outputs and a PLL bandwidth of 2–4 MHz, it achieves ≤0.45 ps RMS jitter - meeting the PCI-SIG Base Specification 4.0 requirement. SI5338A-B06038-GMR also supports SRNS mode for Gen 3 applications.

Can the SI5338A-B06038-GMR generate different output voltages simultaneously?

Yes, SI5338A-B06038-GMR provides four independent VDDOx supplies (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs - enabling direct interfacing with mixed-voltage FPGAs, processors, and SerDes without external level shifters.

How is the SI5338A-B06038-GMR programmed, and what tools are required?

The SI5338A-B06038-GMR is programmed via its I²C/SMBus-compatible interface using Skyworks' ClockBuilder Pro software. This GUI tool generates custom configuration files, validates timing constraints, and exports register maps for production programming. SI5338A-B06038-GMR also supports pin-controlled frequency increment/decrement for runtime adjustments without host intervention.

What package type and pin count does the SI5338A-B06038-GMR use?

The SI5338A-B06038-GMR uses a 24-pin QFN package measuring 4 mm × 4 mm with an exposed thermal pad. It follows the standard Si5338 pinout: six inputs (IN1–IN6), eight differential clock outputs (CLK0A/B through CLK3A/B), four VDDO rails, one VDD core supply, two I²C lines (SCL/SDA), one interrupt (INTR), and multiple GND connections - all documented in Skyworks' Rev. 1.6 datasheet.

SI5338A-B06038-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B06038-GMR FAQ

1.How can I place an order for SI5338A-B06038-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B06038-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B06038-GMR reliable?

The price and inventory of SI5338A-B06038-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B06038-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B06038-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B06038-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B06038-GMR?

SI5338A-B06038-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B06038-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B06038-GMR?

For technical support, including SI5338A-B06038-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B06038-GMR requirements.

6.How does Aetrix verify that SI5338A-B06038-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B06038-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B06038-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B06038-GMR?

All SI5338A-B06038-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B06038-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B06038-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B06038-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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