Skyworks Solutions Inc. SI5338A-B06088-GM
- Part No.:
- SI5338A-B06088-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338A-B06088-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:2,459
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338A-B06088-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency clocks (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and configurable LVPECL/LVDS/HCSL/CMOS outputs. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe switch cards and 10 GbE line cards.
For engineers reviewing the SI5338A-B06088-GM datasheet, SI5338A-B06088-GM pinout, SI5338A-B06088-GM application, or SI5338A-B06088-GM equivalent, key selection criteria include differential output jitter performance at 100 MHz HCSL, spread-spectrum modulation configurability per output, independent VDDO voltage assignment (1.5–3.3 V), and support for external crystal (8–30 MHz) or high-frequency differential inputs (up to 710 MHz).
Technical Context
The SI5338A-B06088-GM implements a two-stage PLL architecture: a high-stability input stage locks to one of six reference inputs (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks. Each output driver supports integer or fractional mode operation with programmable initial phase offset (±45 ns) and glitchless frequency increment/decrement in 1 ppm steps.
Its functional block includes on-chip OTP NVM for configuration storage, I²C/SMBus interface with interrupt (INTR) signaling, loss-of-lock and loss-of-signal alarms, and external feedback capability for zero-delay mode. The device operates across –40 to +85 °C with core supply options of 1.8 V, 2.5 V, or 3.3 V and independent output buffer supplies (VDDO0–VDDO3).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | Four differential clock outputs (CLK0A/B through CLK3A/B); supports LVPECL, LVDS, HCSL, CML, SSTL, HSTL, or CMOS formats |
| Frequency range | 0.16–710 MHz per output; two outputs may exceed 350 MHz simultaneously (Fvco/4 and Fvco/6) |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), measured at 125 MHz LVDS/HCSL with 25 MHz crystal reference |
| PCIe compliance | Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliant; meets PCIe Gen 4 RMS jitter ≤0.45 ps |
| Supply flexibility | Core VDD: 1.8/2.5/3.3 V; independent VDDOx per output: 1.5/1.8/2.5/3.3 V |
| Reference inputs | External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad |
Pinout & Package
SI5338A-B06088-GM uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1/IN2, IN5/IN6 | Differential reference inputs | Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination |
| IN3/IN4 | Single-ended reference inputs | Support CMOS/SSTL/HSTL signals (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A/CLK0B – CLK3A/CLK3B | Differential clock outputs | Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CML with dedicated VDDOx supply |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5–3.3 V supplies per output pair; enable mixed-voltage system interfacing |
| VDD | Core supply | 1.8/2.5/3.3 V ± tolerance; powers PLL, synthesizers, and control logic |
| SCL/SDA | I²C interface | Standard SMBus-compatible serial bus (up to 400 kHz); supports configuration and status readback |
| INTR | Interrupt output | Open-drain alarm signal indicating loss-of-lock or loss-of-signal events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Enables true zero-ppm frequency accuracy on all four outputs with independent fractional-N dividers |
| Per-output spread spectrum | Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz range |
| Glitchless frequency tuning | Pin-controlled or I²C-based frequency increment/decrement in 1 ppm steps without output interruption |
| Programmable phase alignment | Independent phase adjustment per output with <20 ps step resolution and ±45 ns range |
| Zero-delay mode support | External feedback path enables synchronous clock distribution with minimal propagation delay variation |
Applications
| PCIe Switch Timing | Ethernet Line Card Clocking |
|---|---|
Use Scenario: Providing synchronized 100 MHz HCSL clocks to multiple PCIe Gen 4 endpoints and root complexes on a high-density switch ASIC board. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, spread-spectrum-enabled reference clocks meeting PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS). Use Value: Eliminates need for four discrete oscillators; reduces board area and BOM count while maintaining Gen 4 compliance via per-output SSC and precise phase alignment. |
Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10 GbE PHYs and SerDes on telecom line cards with strict EMI requirements. IC Role / Device Role / Timing Role: Programmable frequency translator converting a single 25 MHz crystal reference into multiple high-frequency Ethernet clocks with independent SSC. Use Value: Achieves <0.7 ps RMS jitter at 156.25 MHz while enabling EMI reduction via configurable down-spread on critical outputs. |
| Broadcast Video Synchronization | FPGA/Processor Clock Domain Crossing |
Use Scenario: Distributing frame-locked 74.25 MHz (HD-SDI) and 148.5 MHz (3G-SDI) clocks across video processing modules in broadcast encoders. IC Role / Device Role / Timing Role: Any-frequency clock generator producing exact SMPTE-compliant frequencies from a single 10 MHz OCXO reference. Use Value: Guarantees zero-ppm accuracy across all outputs, eliminating timing drift between video pipelines and enabling deterministic inter-module synchronization. |
Use Scenario: Supplying asynchronous clocks (e.g., 100 MHz, 200 MHz, 300 MHz, 400 MHz) to FPGA fabric, DDR controller, PCIe IP, and ARM processor subsystems. IC Role / Device Role / Timing Role: Configurable quad clock source enabling independent domain clocking with programmable phase offsets for setup/hold optimization. Use Value: Reduces timing closure effort by allowing per-clock skew tuning (<20 ps steps) and eliminates external clock buffers for level translation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B06109-GM | Same silicon, different factory-programmed configuration: preloaded with PCIe Gen 3 SRNS profile and default 100 MHz HCSL outputs | Targeted for plug-and-play PCIe add-in card designs requiring no I²C programming at power-up | Select when boot-time clock availability without host firmware initialization is required |
| LMK04832ISQE/NOPB | Two PLLs (not four independent synthesizers); higher power (120 mA typ); supports JESD204B SYSREF but lacks per-output SSC | Better suited for RF/data converter timing with deterministic latency; less optimal for multi-protocol serial interface consolidation | Select when ultra-low additive jitter (<0.15 ps) and JESD204B support outweigh quad-output flexibility |
Compared with Si5338A-B06109-GM, SI5338A-B06088-GM offers full field programmability via I²C rather than factory-fixed settings, enabling dynamic reconfiguration. Compared with LMK04832ISQE/NOPB, SI5338A-B06088-GM provides finer per-output control (SSC, phase, voltage) at lower power and smaller footprint, though with less deterministic latency for JESD204B.
Availability
SI5338A-B06088-GM is available at Aetrix Electronics and suitable for PCIe switch timing, 10 GbE line cards, broadcast video synchronization, and FPGA clock domain crossing requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5338A-B06088-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs.
The Si5338 product line was designed for high-performance, multi-protocol serial interface timing-enabling consolidation of discrete oscillators and buffers in networking, computing, and communications infrastructure equipment.
FAQ
What is the primary function of the SI5338A-B06088-GM?
The SI5338A-B06088-GM is an I²C-programmable quad-output clock generator using Skyworks' MultiSynth™ technology to synthesize any frequency from 0.16 to 710 MHz on each output with 0.7 ps RMS typical phase jitter. It serves as a flexible, low-jitter timing solution for PCIe, Ethernet, broadcast video, and FPGA applications where multiple precise clock domains are required.
Does the SI5338A-B06088-GM support PCIe Gen 4 timing requirements?
Yes, the SI5338A-B06088-GM meets PCIe Gen 4 Common Clock RMS jitter specifications (≤0.45 ps) when configured with HCSL outputs at 100 MHz and appropriate PLL bandwidth (2–5 MHz). Its jitter performance is validated per PCI-SIG test methodology using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4.
Can the SI5338A-B06088-GM generate different output voltages simultaneously?
Yes, the SI5338A-B06088-GM supports independent output buffer supplies (VDDO0–VDDO3), allowing simultaneous LVPECL (2.5 V), LVDS (1.8 V), HCSL (1.5 V), and CMOS (3.3 V) outputs on its four differential pairs. This enables direct interfacing with mixed-voltage ASICs, FPGAs, and PHYs without external level translators.
How is the SI5338A-B06088-GM programmed and configured?
The SI5338A-B06088-GM is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration includes output format, frequency, VDDO voltage, spread spectrum, phase offset, and alarm thresholds. Factory OTP memory retains settings for immediate operation after power-up.
What reference inputs does the SI5338A-B06088-GM accept?
The SI5338A-B06088-GM accepts six reference input types: external crystal (8–30 MHz), single-ended CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz on IN1/IN2 or IN5/IN6). Input selection and conditioning are fully configurable via I²C registers, supporting flexible system-level clock tree design.
SI5338A-B06088-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338A-B06088-GM FAQ
1.How can I place an order for SI5338A-B06088-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338A-B06088-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338A-B06088-GM reliable?
The price and inventory of SI5338A-B06088-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B06088-GM is usually 5 days.
3.What payment methods are accepted for SI5338A-B06088-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B06088-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338A-B06088-GM?
SI5338A-B06088-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338A-B06088-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338A-B06088-GM?
For technical support, including SI5338A-B06088-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B06088-GM requirements.
6.How does Aetrix verify that SI5338A-B06088-GM is sourced from the original manufacturer or authorized distributors?
All SI5338A-B06088-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B06088-GM meets industry standards.
7.What is the process for return or replacement of SI5338A-B06088-GM?
All SI5338A-B06088-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B06088-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338A-B06088-GM part is unused and in its original packaging.
Return procedure for SI5338A-B06088-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338A-B06088-GM Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

