Skyworks Solutions Inc. SI5338A-B06088-GMR

Overview

SI5338A-B06088-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338A-B06088-GMR datasheet, SI5338A-B06088-GMR pinout, SI5338A-B06088-GMR application, or SI5338A-B06088-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ frequency synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338A-B06088-GMR implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider followed by four independent MultiSynth™ fractional-N synthesizers, each feeding a configurable output driver. Input reference flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) sources.

Each of the four output drivers supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage selection (1.5–3.3 V), programmable phase offset (±45 ns, <20 ps step), and glitchless frequency increment/decrement (1 ppm steps). External feedback mode enables zero-delay operation, and status monitoring includes INTR pin assertion for loss-of-lock and loss-of-signal events.

Key Specifications

Pinout & Package

SI5338A-B06088-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338A-B06109-GM, SI5338A-B06088-GMR delivers identical silicon performance but with factory-tuned register settings for specific output frequencies and formats; versus LMK04832ISQE/NOPB, it trades JESD204B features for PCIe Gen 4 compliance, lower power, and 24-QFN compactness-making it optimal for space-constrained, high-throughput serial link timing.

Availability

SI5338A-B06088-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and broadcast video timing requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338A-B06088-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable any-frequency clock generation for high-speed serial interfaces, designed specifically to replace multiple fixed-frequency oscillators while meeting stringent jitter and compliance requirements of PCIe, Ethernet, and broadcast video systems.

FAQ

What is the primary function of the SI5338A-B06088-GMR in a PCIe Gen 4 system?

The SI5338A-B06088-GMR serves as a quad-output clock generator that provides four low-jitter, independently configurable reference clocks (e.g., 100 MHz HCSL) to PCIe Gen 4 switches or endpoints. It meets PCIe Gen 4 Common Clock and SRNS jitter specifications (0.15–0.45 ps RMS), supports spread-spectrum clocking to reduce EMI, and enables hardware-based glitchless frequency tuning-making it ideal for high-density, high-reliability PCIe timing architectures where multiple synchronized clocks are required.

Does the SI5338A-B06088-GMR support both differential and single-ended output formats simultaneously?

Yes, the SI5338A-B06088-GMR supports mixed-mode output configurations: up to four differential outputs (LVPECL/LVDS/HCSL/CML) and up to eight single-ended outputs (CMOS/SSTL/HSTL), or any combination thereof, with independent voltage selection per output bank (VDDO0–VDDO3). Each output driver is fully configurable via I²C or hardware pins, allowing simultaneous use of LVDS for SerDes lanes and CMOS for control logic on the same device.

How is the SI5338A-B06088-GMR programmed, and what tools are required?

The SI5338A-B06088-GMR is programmed via its I²C/SMBus-compatible serial interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. This GUI tool allows engineers to configure output frequencies, formats, voltages, spread-spectrum parameters, phase offsets, and alarm thresholds, then generate custom configuration files for factory programming or in-system reprogramming. No external hardware programmer is needed-only a USB-to-I²C adapter and ClockBuilder Pro (freely downloadable from skyworksinc.com).

What is the significance of the "B06088" suffix in SI5338A-B06088-GMR?

The "B06088" suffix identifies a factory-programmed configuration variant of the SI5338A die, specifying a predefined set of register values for output frequencies, formats, and other timing parameters. It is not a revision code or package identifier. The "GMR" denotes the 24-QFN RoHS-compliant package with green molding compound. Users requiring different configurations may select blank variants (e.g., SI5338A-A01879-GM) and program them using ClockBuilder Pro.

Can the SI5338A-B06088-GMR operate in clock buffer (PLL bypass) mode, and what are its benefits?

Yes, the SI5338A-B06088-GMR supports clock buffer mode (PLL bypass), where input clocks pass directly to outputs with minimal additive jitter (0.165 ps RMS typical, 12 kHz–20 MHz). This mode eliminates PLL-induced noise and enables ultra-low-latency signal distribution-ideal for applications requiring deterministic propagation delay (e.g., 2.5–4 ns) and preservation of input clock integrity, such as high-speed test equipment or legacy system upgrades where PLL phase alignment is unnecessary.