Skyworks Solutions Inc. SI5338A-B06137-GM

Overview

SI5338A-B06137-GM from Skyworks Solutions is an I²C-programmable, quad-output clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typical phase jitter), supporting LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL outputs up to 710 MHz, and operating from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces multiple crystal oscillators in PCIe Gen 1–4, Ethernet switch/router, and FPGA clocking systems.

For engineers reviewing the SI5338A-B06137-GM datasheet, SI5338A-B06137-GM pinout, SI5338A-B06137-GM application, or SI5338A-B06137-GM equivalent, key selection considerations include PCIe Gen 4 SRNS compliance, independent per-output voltage configuration (1.5–3.3 V), 1 ppm frequency increment/decrement, <20 ps phase step resolution, and spread-spectrum control across any output.

Technical Context

The SI5338A-B06137-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each feeding a configurable output driver. Its input flexibility supports external crystals (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential clocks (5–710 MHz).

Each of the four differential output pairs (CLK0A/B through CLK3A/B) supports independent format selection, voltage rail assignment (VDDO0–VDDO3), phase offset (±45 ns), and spread-spectrum modulation (0.5–5.0% at 33–63 kHz). Loss-of-lock and loss-of-signal alarms are provided via the INTR pin.

Key Specifications

Pinout & Package

SI5338A-B06137-GM uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left (IN1), pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with Si5338A-B06136-GM, SI5338A-B06137-GM offers field-programmable flexibility via I²C, while LMK04832RHAT trades configurability for JESD204B-specific features and higher integration in ADC/DAC timing chains-making SI5338A-B06137-GM optimal for PCIe/Ethernet/FPGA platforms demanding compact, multi-voltage, low-jitter synthesis.

Availability

SI5338A-B06137-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch fabric, 10GbE line cards, and broadcast video router designs requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338A-B06137-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs for infrastructure, automotive, and mobile markets.

The Si5338 family is designed as a programmable, low-jitter clock generator platform targeting high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-where flexible frequency synthesis and multi-format output drive system-level timing consolidation.

FAQ

What is the primary function of the SI5338A-B06137-GM in a PCIe Gen 4 system?

The SI5338A-B06137-GM serves as a quad-output clock generator that delivers four independent, low-jitter (0.15–0.45 ps RMS) reference clocks compliant with PCIe Gen 4 Common Clock and SRNS specifications. It replaces multiple discrete oscillators, reduces board space, and enables precise phase alignment across SerDes lanes-critical for maintaining signal integrity in high-speed switch fabrics where SI5338A-B06137-GM operates with a 2–5 MHz PLL bandwidth and CDR = 10 MHz.

Does the SI5338A-B06137-GM support different output voltage levels on each clock channel?

Yes, the SI5338A-B06137-GM supports independent output voltage configuration per channel via VDDO0–VDDO3 rails, each selectable between 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows direct interfacing with mixed-voltage devices-for example, driving 1.8 V LVDS FPGA transceivers and 2.5 V Ethernet PHYs simultaneously-without external level shifters, a capability confirmed in Table 6 and Section 3.4 of the official datasheet.

Can the SI5338A-B06137-GM generate frequencies above 350 MHz on all four outputs simultaneously?

No. While the SI5338A-B06137-GM supports up to 710 MHz on individual outputs, only two unique frequencies above 350 MHz can be generated simultaneously-specifically Fvco/4 and Fvco/6-as stated in Note 6 of Table 6. Higher-frequency outputs must share these two synthesis paths, limiting concurrent >350 MHz generation to two channels; the remaining outputs must operate below 350 MHz or use integer-related frequencies within the same synthesis stage.

How does the SI5338A-B06137-GM handle loss-of-signal detection?

The SI5338A-B06137-GM provides hardware-based loss-of-signal (LOS) detection on all six clock inputs (IN1–IN6), with detection time of 2.6–5 µs and release time of 0.01–1 µs (Table 5). When triggered, it asserts the open-drain INTR pin to signal host processors or monitoring logic. This feature is active in both PLL and buffer modes, though LOS functionality is disabled below 1 MHz in buffer mode per datasheet footnote.

Is ClockBuilder Pro software required to configure the SI5338A-B06137-GM?

While ClockBuilder Pro is the recommended GUI tool for rapid configuration and validation of the SI5338A-B06137-GM, full I²C register-level programming is supported per Section 5 and Register Map (Section 6) of the datasheet. Engineers may implement custom firmware to write to the 256-byte register space directly-enabling boot-time initialization without PC dependency-provided timing constraints (e.g., 667 ns pin-controlled updates) and register dependencies are observed in SI5338A-B06137-GM implementation.