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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B06137-GMR

Name: SI5338A-B06137-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B06137-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B06137-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B06137-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338A-B06137-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications including PCIe, Ethernet, and FPGA clocking.

For engineers reviewing the SI5338A-B06137-GMR datasheet, SI5338A-B06137-GMR pinout, SI5338A-B06137-GMR application, or SI5338A-B06137-GMR equivalent, key selection criteria include its MultiSynth™ any-frequency synthesis capability (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum control (0.5–5.0% down-spread), and 24-QFN package compatibility with space-constrained PCB layouts.

Technical Context

The SI5338A-B06137-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each feeding a configurable output driver. Its input flexibility supports external crystals (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential clocks (5–710 MHz).

Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage rails (VDDO0–VDDO3), programmable phase offset (±45 ns), and glitchless frequency increment/decrement in 1 ppm steps. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring via the INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 4 common clock jitter requirements (≤0.45 ps RMS) when configured per spec
Output Frequency Range	0.16–710 MHz - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, Fibre Channel 1.0625 GHz (via Fvco/4)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), differential (5–710 MHz) - enables flexible system-level clock sourcing
Output Formats	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - allows direct interface to FPGAs, ASICs, and SerDes without level-shifting
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.5/1.8/2.5/3.3 V - supports mixed-voltage SoC and FPGA domains
Package	24-pin QFN, 4 × 4 mm - surface-mount compatible with automated assembly and thermal pad for 10°C/W junction-to-case dissipation
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments

Pinout & Package

SI5338A-B06137-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C) and provides 37°C/W junction-to-ambient thermal resistance in still air.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled LVDS/LVPECL/CML references up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B–CLK3A/CLK3B	Differential output pairs	Four independent output drivers; each pair configurable as LVPECL/LVDS/HCSL/CML with dedicated VDDO rail
VDDO0–VDDO3	Output buffer supply pins	Enable per-output voltage setting (1.5/1.8/2.5/3.3 V) for mixed-signal interface compatibility
SCL, SDA	I²C/SMBus interface	Standard 100 kHz / 400 kHz operation; supports ClockBuilder Pro programming and runtime configuration
INTR	Interrupt output	Open-drain status pin asserting on loss-of-lock or loss-of-signal events; requires 1 kΩ pull-up

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling zero-ppm accuracy at any output frequency between 0.16–710 MHz
PCIe Gen 3 SRNS compliance	Meets <0.32 ps RMS jitter requirement under separate reference no-spread conditions (2–5 MHz PLL BW, 10 MHz CDR)
Independent phase adjustment	±45 ns range in <20 ps steps per output - enables precise skew alignment across multi-lane SerDes interfaces
Spread spectrum control	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output - reduces EMI peak emissions
Glitchless frequency tuning	1 ppm step size with pin-controlled increment/decrement - enables dynamic clock scaling without output interruption

Applications

PCIe Gen 4 Root Complex Timing	Ethernet Switch Clock Distribution
Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe Gen 4 endpoints and root ports in server motherboard designs. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter reference clocks with matched propagation delay and programmable phase alignment. Use Value: Enables compliance with PCIe Gen 4 total jitter limit (≤33.6 ps pk-pk) while eliminating four discrete XO footprints and reducing BOM count.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet buffers, and switch fabric controllers in Layer-3 switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing integer-related frequencies from a single 25 MHz crystal reference. Use Value: Reduces board area by 60% vs. discrete oscillator solution and supports IEEE 802.3bj jitter requirements (<0.7 ps RMS) via optimized MultiSynth™ integer-mode operation.
FPGA/ASIC Clock Tree Synthesis	Broadcast Video Timing Generator
Use Scenario: Supplying multiple domain clocks (e.g., 200 MHz logic, 400 MHz transceiver, 100 MHz DDR) to Xilinx Versal or Intel Agilex FPGAs. IC Role / Device Role / Timing Role: Configurable clock generator with independent VDDO rails and format selection per output channel. Use Value: Eliminates need for external level shifters and fanout buffers; supports simultaneous LVDS (transceiver), HCSL (memory), and CMOS (logic) signaling standards.	Use Scenario: Generating SMPTE ST 2082 (12G-SDI) 74.25 MHz, ST 2081 (6G-SDI) 37.125 MHz, and ST 292 (HD-SDI) 27 MHz clocks from one device in broadcast camera processing units. IC Role / Device Role / Timing Role: Low-phase-noise clock source meeting SMPTE ST 2059-2 wander and jitter specifications. Use Value: Achieves <10 ps pk-pk period jitter at 74.25 MHz - satisfies SMPTE ST 2059-2 Class A timing stability requirements for professional video infrastructure.

PCIe Gen 4 Root Complex Timing

Ethernet Switch Clock Distribution

Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe Gen 4 endpoints and root ports in server motherboard designs.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter reference clocks with matched propagation delay and programmable phase alignment.

Use Value: Enables compliance with PCIe Gen 4 total jitter limit (≤33.6 ps pk-pk) while eliminating four discrete XO footprints and reducing BOM count.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet buffers, and switch fabric controllers in Layer-3 switches.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing integer-related frequencies from a single 25 MHz crystal reference.

Use Value: Reduces board area by 60% vs. discrete oscillator solution and supports IEEE 802.3bj jitter requirements (<0.7 ps RMS) via optimized MultiSynth™ integer-mode operation.

FPGA/ASIC Clock Tree Synthesis

Broadcast Video Timing Generator

Use Scenario: Supplying multiple domain clocks (e.g., 200 MHz logic, 400 MHz transceiver, 100 MHz DDR) to Xilinx Versal or Intel Agilex FPGAs.

IC Role / Device Role / Timing Role: Configurable clock generator with independent VDDO rails and format selection per output channel.

Use Value: Eliminates need for external level shifters and fanout buffers; supports simultaneous LVDS (transceiver), HCSL (memory), and CMOS (logic) signaling standards.

Use Scenario: Generating SMPTE ST 2082 (12G-SDI) 74.25 MHz, ST 2081 (6G-SDI) 37.125 MHz, and ST 292 (HD-SDI) 27 MHz clocks from one device in broadcast camera processing units.

IC Role / Device Role / Timing Role: Low-phase-noise clock source meeting SMPTE ST 2059-2 wander and jitter specifications.

Use Value: Achieves <10 ps pk-pk period jitter at 74.25 MHz - satisfies SMPTE ST 2059-2 Class A timing stability requirements for professional video infrastructure.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06137-GM	Higher integration: integrated crystal, lower jitter (0.35 ps RMS), 12-output capability, but larger 32-QFN package	Preferred for new designs requiring ultra-low jitter and crystal-free BOM; not drop-in due to pin count and footprint change	Select when jitter budget is <0.4 ps RMS and crystal integration simplifies layout; verify thermal derating for 32-QFN
ICS853S01AGI-01LFT	Fixed-frequency, non-programmable quad LVDS generator; 0.9 ps RMS jitter; 3.3 V only; no spread spectrum or phase control	Suitable for cost-sensitive, static-clock applications where frequency agility is unnecessary	Choose for legacy systems with fixed 100/125 MHz requirements and no need for I²C reconfiguration or EMI reduction features

Compared with Si5332A-D06137-GM and ICS853S01AGI-01LFT, the SI5338A-B06137-GMR uniquely balances field-programmability, jitter performance, and 24-QFN compactness-making it optimal for PCIe Gen 4 add-in cards and FPGA-based edge compute platforms where design flexibility and board space are constrained.

Availability

SI5338A-B06137-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, Ethernet switch/router clock distribution, and FPGA/ASIC clock tree synthesis requiring stable component supply and long-term production continuity.

Supply support for SI5338A-B06137-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-enabling system architects to consolidate timing functions into a single configurable IC.

FAQ

What is the maximum output frequency supported by SI5338A-B06137-GMR?

The SI5338A-B06137-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, and 250 MHz on HCSL. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) due to VCO architecture constraints. All outputs maintain ≤1 ps RMS jitter at 100 MHz and meet PCIe Gen 4 jitter specs when configured per AN562 guidelines.

Does SI5338A-B06137-GMR support spread-spectrum clocking (SSC)?

Yes, SI5338A-B06137-GMR supports fully programmable spread-spectrum clocking on any output: spread range 0.5–5.0% down-spread, modulation rate 33–63 kHz, and selectable center-spread or down-spread modes. SSC is enabled per-output via I²C register writes and does not affect other channels. Default factory setting is 0.5% down-spread at ~31.5 kHz.

Can SI5338A-B06137-GMR operate without an external crystal?

Yes, SI5338A-B06137-GMR can accept external CMOS, SSTL, HSTL, or differential clock inputs (5–710 MHz) directly on IN3–IN6 pins, bypassing the internal crystal oscillator circuit. When using external reference, the crystal pins (IN1/IN2) are unused. Crystal mode remains optional and supports 8–30 MHz fundamental-mode crystals with on-chip load capacitance tuning.

What is the power consumption of SI5338A-B06137-GMR under full-load conditions?

At 100 MHz on all four outputs with a 25 MHz reference clock, SI5338A-B06137-GMR draws 45 mA typical core current (VDD = 3.3 V), plus output buffer current up to 30 mA per LVPECL driver. Total typical supply current is ≤165 mA. In buffer-only (PLL-bypass) mode with 50 MHz reference, core current drops to 12 mA, enabling ultra-low-power standby timing.

How is SI5338A-B06137-GMR programmed and configured?

SI5338A-B06137-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software, which auto-generates register maps based on user-defined frequency, format, and voltage requirements. Configuration can be stored in on-chip OTP NVM for power-on initialization, or loaded dynamically during operation for reconfigurable timing schemes.

SI5338A-B06137-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B06137-GMR FAQ

1.How can I place an order for SI5338A-B06137-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B06137-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B06137-GMR reliable?

The price and inventory of SI5338A-B06137-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B06137-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B06137-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B06137-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B06137-GMR?

SI5338A-B06137-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B06137-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B06137-GMR?

For technical support, including SI5338A-B06137-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B06137-GMR requirements.

6.How does Aetrix verify that SI5338A-B06137-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B06137-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B06137-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B06137-GMR?

All SI5338A-B06137-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B06137-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B06137-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B06137-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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