Skyworks Solutions Inc. SI5338A-B07234-GM
- Part No.:
- SI5338A-B07234-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338A-B07234-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338A-B07234-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in FPGA, processor, and Ethernet switch timing systems.
For engineers reviewing the SI5338A-B07234-GM datasheet, SI5338A-B07234-GM pinout, SI5338A-B07234-GM application, or SI5338A-B07234-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro software integration.
Technical Context
The SI5338A-B07234-GM implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each synthesizer supports integer or fractional mode, enabling true zero-ppm frequency accuracy and <20 ps programmable phase offset steps.
Its output stage provides per-driver configurability for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, with independent VDDO supplies and on-chip termination. The device supports external feedback for zero-delay mode, loss-of-lock and loss-of-signal alarms, and glitchless frequency increment/decrement in 1 ppm steps via pin control or I²C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements at 125 MHz output |
| Output Frequency Range | 0.16–710 MHz - covers PCIe (100 MHz), Ethernet (125/156.25 MHz), Fibre Channel (1.0625 GHz derived), and broadcast video (27/74.25 MHz) |
| Input Flexibility | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables reuse of existing reference sources |
| Supply Voltages | VDD = 1.8/2.5/3.3 V; VDDOx = 1.4–3.63 V - supports mixed-voltage system clocking without level shifters |
| Temperature Range | –40 to +85 °C - qualified for industrial and telecom line card environments |
| Package | 24-pin QFN, 4 × 4 mm - space-constrained PCBs with thermal resistance θJA = 37 °C/W |
Pinout & Package
SI5338A-B07234-GM uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). Package conforms to JEDEC MO-220, with 0.5 mm pitch and 0.8 mm max height.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination |
| IN3, IN4 | Single-ended input pins | Support 5–200 MHz CMOS inputs; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A/CLK0B to CLK3A/CLK3B | Differential output pairs | Four independent outputs; each configurable as LVPECL/LVDS/HCSL/CML with per-output VDDO |
| VDDO0–VDDO3 | Output buffer supply rails | Enable mixed-signal clock distribution (e.g., 1.8 V LVDS to FPGA, 3.3 V CMOS to microcontroller) |
| SCL, SDA, INTR | I²C interface & interrupt | SMBus-compatible 100/400 kHz interface; INTR asserts on LOS/LOL events |
| VDD | Core supply | 1.8/2.5/3.3 V ±10%; IDD = 45 mA typ @ 100 MHz all outputs |
| GND, RSVD_GND | Ground connections | Multiple GND pins and thermal pad ensure low-noise reference and thermal dissipation |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enable simultaneous generation of unrelated frequencies (e.g., 100 MHz PCIe + 125 MHz Ethernet + 156.25 MHz SerDes + 27 MHz video) with 0 ppm error |
| PCIe Gen 1–4 compliance | Meets Common Clock jitter specs (≤0.45 ps RMS Gen 3/4) and SRNS requirements without external filtering |
| Programmable spread spectrum | Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI in dense PCB layouts |
| Independent phase adjustment | ±45 ns range in <20 ps steps per output - enables precise skew alignment across multi-lane interfaces (e.g., DDR, PCIe) |
| Glitchless frequency tuning | 1 ppm step size via PINC/FINC pins or I²C - allows real-time clock rate adaptation without output interruption |
Applications
| PCIe Gen 3/4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: Providing synchronized 100 MHz common clock and 100 MHz reference clock to PCIe Gen 3/4 switches and endpoint devices in server backplanes. IC Role / Device Role / Timing Role: Quad clock generator delivering PCIe-compliant clocks with sub-0.5 ps RMS jitter and SRNS support. Use Value: Eliminates need for four discrete oscillators while meeting PCIe Base Spec 3.0/4.0 jitter masks and reducing BOM count by 75%. | Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet processors in Layer 3 switches. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer supporting IEEE 802.3 standards with low additive jitter in buffer mode. Use Value: Enables single-device timing for multi-rate Ethernet ports, reducing layout complexity and improving inter-port skew control. |
| Broadcast Video/Audio Sync | FPGA & Processor Clocking |
Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks to SDI transceivers and video processing FPGAs in broadcast encoders. IC Role / Device Role / Timing Role: Low-jitter, multi-format clock source with independent output voltage and format per channel. Use Value: Supports mixed-interface video subsystems (LVDS for FPGAs, CMOS for microcontrollers) without external level translation. | Use Scenario: Supplying core, memory, and peripheral clocks (e.g., 500 MHz ARM core, 200 MHz DDR3, 48 MHz USB) to heterogeneous SoCs and FPGA-based compute modules. IC Role / Device Role / Timing Role: Configurable quad clock generator with independent frequency, format, and voltage per output driver. Use Value: Replaces multiple fixed-frequency oscillators and buffers, simplifying power domain isolation and reducing board area by >60%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D07234-GM | Higher integration: includes integrated LDOs, enhanced jitter performance (0.35 ps RMS), and extended frequency range up to 3.2 GHz on two outputs | Targeted at high-speed SerDes (PCIe Gen 5, 112G PAM4) where ultra-low jitter and higher frequencies are required | Select Si5332A-D07234-GM when upgrading to Gen 5 infrastructure or requiring integrated power regulation |
| ICS853S01AG-01LF | Fixed-frequency, non-programmable quad LVDS clock generator; no I²C interface or MultiSynth™ flexibility | Used in cost-sensitive, static-clock applications where only standard frequencies (e.g., 100/125/156.25 MHz) are needed | Choose ICS853S01AG-01LF for production designs with unchanging clock trees and strict BOM cost targets |
Compared with Si5332A-D07234-GM and ICS853S01AG-01LF, SI5338A-B07234-GM delivers optimal balance of programmability, jitter performance, and industrial temperature support for PCIe Gen 3/4, Ethernet, and broadcast video systems - offering field-upgradable timing without hardware redesign.
Availability
SI5338A-B07234-GM is available at Aetrix Electronics and suitable for PCIe switch timing, Ethernet routing, broadcast video synchronization, and FPGA clocking applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5338A-B07234-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for wireless, automotive, and infrastructure markets.
The Si5338 product line was designed to replace multiple crystal oscillators in high-performance digital systems, delivering programmable, low-jitter clock synthesis for PCIe, Ethernet, and broadcast video applications with minimal board space and design effort.
FAQ
What is the maximum output frequency supported by SI5338A-B07234-GM in LVPECL format?
The SI5338A-B07234-GM supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the datasheet. This capability enables direct clocking of high-speed SerDes lanes and 10G/25G Ethernet PHYs without frequency multiplication. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6), and requires proper termination with 100 Ω differential loads. SI5338A-B07234-GM maintains 0.7 ps RMS jitter even at these frequencies when driven by a low-noise differential reference.
Does SI5338A-B07234-GM support PCIe Gen 4 Common Clock compliance?
Yes, SI5338A-B07234-GM meets PCIe Gen 4 Common Clock jitter requirements with ≤0.45 ps RMS (10 kHz–50 MHz) as specified in Table 12. This compliance is achieved using a PLL bandwidth of 2–4 MHz and CDR = 10 MHz, and is validated with the Skyworks PCIe Clock Jitter Tool. SI5338A-B07234-GM also satisfies Gen 1/2/3 Common Clock and Gen 3 SRNS specifications, making it suitable for backward- and forward-compatible server and storage platforms.
Can SI5338A-B07234-GM generate different output voltages on each channel?
Yes, SI5338A-B07234-GM provides independent VDDO0–VDDO3 supply pins, allowing each of its four output drivers to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage components - for example, 1.8 V LVDS to an FPGA bank and 3.3 V CMOS to a microcontroller - without external level shifters. The SI5338A-B07234-GM datasheet specifies VDDOx tolerance from 1.4 V to 3.63 V, ensuring robust operation across process and temperature variations.
How is SI5338A-B07234-GM programmed, and is ClockBuilder Pro required?
SI5338A-B07234-GM is programmed via an I²C/SMBus-compatible serial interface (SCL/SDA pins) operating at 100 kHz or 400 kHz. While ClockBuilder Pro software from Skyworks simplifies configuration, register-level programming is fully documented in the datasheet (Section 6) and supported by third-party tools. SI5338A-B07234-GM includes factory-programmed OTP NVM, allowing pre-configured startup behavior without host intervention - ideal for boot-critical timing in embedded systems.
What input reference sources are compatible with SI5338A-B07234-GM?
SI5338A-B07234-GM accepts six input types: (1) 8–30 MHz fundamental-mode crystals on IN1/IN2, (2) 5–200 MHz CMOS clocks on IN3/IN4, (3) 5–350 MHz SSTL/HSTL signals, and (4) 5–710 MHz differential clocks on IN1/IN2 or IN5/IN6. All inputs support automatic loss-of-signal detection with 2.6–5 µs response time. SI5338A-B07234-GM's flexible input stage eliminates need for external signal conditioning in most applications.
SI5338A-B07234-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338A-B07234-GM FAQ
1.How can I place an order for SI5338A-B07234-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338A-B07234-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338A-B07234-GM reliable?
The price and inventory of SI5338A-B07234-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B07234-GM is usually 5 days.
3.What payment methods are accepted for SI5338A-B07234-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B07234-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338A-B07234-GM?
SI5338A-B07234-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338A-B07234-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338A-B07234-GM?
For technical support, including SI5338A-B07234-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B07234-GM requirements.
6.How does Aetrix verify that SI5338A-B07234-GM is sourced from the original manufacturer or authorized distributors?
All SI5338A-B07234-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B07234-GM meets industry standards.
7.What is the process for return or replacement of SI5338A-B07234-GM?
All SI5338A-B07234-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B07234-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338A-B07234-GM part is unused and in its original packaging.
Return procedure for SI5338A-B07234-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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