Skyworks Solutions Inc. SI5338A-B07234-GMR
- Part No.:
- SI5338A-B07234-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338A-B07234-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338A-B07234-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed Ethernet switch/router and FPGA clocking systems.
For engineers reviewing the SI5338A-B07234-GMR datasheet, SI5338A-B07234-GMR pinout, SI5338A-B07234-GMR application, or SI5338A-B07234-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis, independent per-output voltage (1.5/1.8/2.5/3.3 V), ±20 ps phase step resolution, and 24-pin 4×4 mm QFN package with I²C/SMBus configuration interface.
Technical Context
The SI5338A-B07234-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) feeding a fractional-N MultiSynth™ synthesis stage per output. Each of the four outputs has dedicated M/N/P dividers, enabling independent frequency, phase, spread-spectrum, and format configuration without inter-channel coupling.
It supports flexible reference inputs - 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential - and delivers true zero-ppm accuracy on all outputs via programmable integer/fractional synthesis. Loss-of-lock and loss-of-signal alarms, plus independent OEB/PINC/FINC control pins, enable robust system-level timing supervision.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS). |
| Output Frequency Range | 0.16–710 MHz per channel; supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz. |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz). |
| Output Voltage Per Driver | Independently configurable: 1.5 V, 1.8 V, 2.5 V, or 3.3 V - enables mixed-voltage system clock distribution. |
| Phase Adjustment Resolution | <20 ps step size with ±45 ns range - enables fine-grained skew compensation between FPGAs or SerDes lanes. |
| Spread Spectrum | Configurable per output: 0.5–5.0% down-spread, 33–63 kHz modulation rate - reduces EMI in dense PCB layouts. |
| Supply Voltage | Core: 1.8 V / 2.5 V / 3.3 V (±10%); Output buffers: 1.4–3.63 V - simplifies power domain partitioning. |
Pinout & Package
SI5338A-B07234-GMR is housed in a 24-lead, 4 mm × 4 mm, 0.5 mm pitch QFN package with exposed thermal pad. Pin 1 is top-left (IN1), and pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential clock inputs | Accept 5–710 MHz AC-coupled differential references; require external 100 Ω termination. |
| IN3, IN4 | Single-ended clock inputs | Support 5–200 MHz CMOS; VIH = 0.7×VDD, VIL = 0.3×VDD - compatible with standard logic families. |
| CLK0A/CLK0B – CLK3A/CLK3B | Differential output pairs | Four independent LVPECL/LVDS/HCSL/CML outputs; each pair shares VDDOx supply rail. |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.4–3.63 V rails per output group - enables mixed-signal voltage level translation. |
| SCL, SDA, INTR | I²C interface & interrupt | Standard SMBus-compatible 1.8/2.5/3.3 V I/O; INTR asserts open-drain alarm on LOS/LOL events. |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Any-Frequency Synthesis | Generates four independent, zero-ppm-accurate clocks from one reference - eliminates need for multiple XO/VCXO components. |
| PCIe Gen 1–4 & SRNS Compliance | Fully satisfies PCIe Gen 3 Separate Reference No Spread (SRNS) and Gen 4 common clock jitter requirements - validated per Intel Clock Jitter Tool v1.6.4. |
| Independent Output Configuration | Each output supports unique format (LVPECL/LVDS/HCSL/CMOS), frequency, voltage, phase offset, and spread-spectrum settings - enables single-device clock tree for heterogeneous SoCs. |
| Glitchless Frequency Tuning | 1 ppm frequency increment/decrement steps via PINC/FINC pins - enables real-time dynamic clock scaling without output interruption. |
| External Feedback Mode | Supports zero-delay mode by routing CLKOUT back to feedback input - critical for deterministic latency applications like industrial Ethernet. |
Applications
| Ethernet Switch/Routing Timing | PCIe Gen 3/4 Clock Distribution |
|---|---|
Use Scenario: 10 GbE line card requiring synchronized 156.25 MHz, 312.5 MHz, and 625 MHz clocks for MAC, PHY, and SerDes blocks. IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, phase-aligned outputs with independent voltage and format control. Use Value: Replaces three discrete oscillators and one buffer; achieves <0.7 ps RMS jitter at 156.25 MHz, meeting IEEE 802.3bj CAUI-4 spec. | Use Scenario: Server motherboard with dual CPU sockets and multiple PCIe Gen 4 x16 slots needing common-reference clocking. IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering 100 MHz common clock to all slots and 100 MHz SRNS reference to CPUs. Use Value: Meets PCIe Gen 4 common clock TJ ≤33.6 ps pk-pk and SRNS RMS jitter ≤0.32 ps - validated using Skyworks PCIe Jitter Tool. |
| Broadcast Video/Audio Sync | FPGA & Processor Clocking |
Use Scenario: SMPTE 2110 IP video router requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with sub-20 ps inter-output skew. IC Role / Device Role / Timing Role: Multi-format clock synthesizer generating LVDS and HCSL outputs with programmable phase offsets. Use Value: Achieves <100 ps output-to-output skew and <0.7 ps RMS jitter - satisfies SMPTE ST 2110-10 synchronization tolerance. | Use Scenario: Xilinx Versal ACAP-based AI accelerator board needing 300 MHz PL clock, 500 MHz PS clock, 100 MHz DDR4 clock, and 25 MHz debug clock. IC Role / Device Role / Timing Role: Configurable clock source supporting mixed-voltage (1.8 V/2.5 V/3.3 V) and mixed-format (LVDS/CMOS/HCSL) outputs. Use Value: Eliminates four separate clock ICs; enables per-rail voltage optimization and independent spread-spectrum control to reduce system EMI. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B07235-GMR | Same silicon, factory-programmed with different default configuration (different frequency plan and output format mapping). | Pre-configured for telecom line card use cases; requires no initial I²C programming for basic operation. | Select when rapid bring-up without ClockBuilder Pro is required; not suitable for custom multi-frequency synthesis. |
| LMK04832ISQE/NOPB | Two PLLs + eight outputs; higher power (95 mA typ); supports JESD204B SYSREF; no integrated crystal driver. | Targeted at JESD204B converter timing; lacks Si5338's crystal oscillator integration and compact 4×4 mm footprint. | Select for RF/data converter systems needing deterministic SYSREF alignment; avoid if board space or crystal-less design is critical. |
Compared with SI5338A-B07234-GMR, the B07235 variant offers plug-and-play deployment but sacrifices runtime configurability, while the LMK04832 provides superior JESD204B features at the cost of size, power, and crystal dependency - making SI5338A-B07234-GMR optimal for space-constrained, multi-protocol embedded timing.
Availability
SI5338A-B07234-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 server boards, broadcast video routers, and FPGA-based AI accelerators requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338A-B07234-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The Si5338 family is engineered for high-density, multi-protocol timing consolidation - enabling single-chip replacement of multiple oscillators and buffers in networking, computing, and broadcast equipment where low jitter, configurability, and small footprint are critical.
FAQ
What is the primary function of the SI5338A-B07234-GMR in a timing architecture?
The SI5338A-B07234-GMR serves as an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output clocks from a single reference. Its core function is to replace multiple discrete oscillators or buffers in systems such as PCIe Gen 4 servers and 10 GbE switches, delivering frequencies from 0.16 MHz to 710 MHz with 0.7 ps RMS jitter and zero-ppm accuracy. SI5338A-B07234-GMR integrates MultiSynth™ technology to enable per-output format, voltage, phase, and spread-spectrum control - making it ideal for heterogeneous timing domains.
Does the SI5338A-B07234-GMR support PCIe Gen 4 Common Clock compliance?
Yes, the SI5338A-B07234-GMR meets PCIe Gen 4 Common Clock jitter specifications with ≤0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks' validated reference design. This compliance is confirmed in Table 12 of the official datasheet and verified using the Skyworks PCIe Clock Jitter Tool v1.6.4. SI5338A-B07234-GMR achieves this with a PLL loop bandwidth of 2–5 MHz and supports both common clock and SRNS modes - essential for high-speed server and accelerator applications.
Can the SI5338A-B07234-GMR operate without an external crystal?
Yes, the SI5338A-B07234-GMR supports multiple reference sources beyond crystals: CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) inputs. While it includes on-chip crystal oscillator circuitry for 8–30 MHz crystals, it can be used in crystal-less configurations by driving IN3/IN4 or IN1/IN2 with an external clock. SI5338A-B07234-GMR retains full functionality - including jitter performance and MultiSynth™ synthesis - in all reference modes.
How is output voltage configured on the SI5338A-B07234-GMR?
Each of the four output banks (CLK0, CLK1, CLK2, CLK3) has a dedicated VDDOx supply pin (VDDO0–VDDO3), allowing independent voltage assignment per bank: 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This is set externally via board-level regulators - not programmed - and determines the output swing and logic threshold. SI5338A-B07234-GMR uses these voltages to configure LVPECL, LVDS, HCSL, or CMOS output levels automatically, enabling mixed-voltage clock trees without level shifters.
What software tools are required to configure the SI5338A-B07234-GMR?
The SI5338A-B07234-GMR is configured using Skyworks' ClockBuilder Pro software - a free, Windows-based GUI tool that generates register maps, validates frequency plans, and exports I²C initialization scripts. ClockBuilder Pro supports full device simulation, jitter estimation, and hardware validation via USB-to-I²C adapters. SI5338A-B07234-GMR does not require proprietary programmers; standard I²C controllers (e.g., MCU GPIOs or dedicated bridges) can load the generated configuration during boot.
SI5338A-B07234-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338A-B07234-GMR FAQ
1.How can I place an order for SI5338A-B07234-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338A-B07234-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338A-B07234-GMR reliable?
The price and inventory of SI5338A-B07234-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B07234-GMR is usually 5 days.
3.What payment methods are accepted for SI5338A-B07234-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B07234-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338A-B07234-GMR?
SI5338A-B07234-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338A-B07234-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338A-B07234-GMR?
For technical support, including SI5338A-B07234-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B07234-GMR requirements.
6.How does Aetrix verify that SI5338A-B07234-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338A-B07234-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B07234-GMR meets industry standards.
7.What is the process for return or replacement of SI5338A-B07234-GMR?
All SI5338A-B07234-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B07234-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338A-B07234-GMR part is unused and in its original packaging.
Return procedure for SI5338A-B07234-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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