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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B07958-GM

Name: SI5338A-B07958-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B07958-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B07958-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B07958-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338A-B07958-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and Ethernet switch fabric.

For engineers reviewing the SI5338A-B07958-GM datasheet, SI5338A-B07958-GM pinout, SI5338A-B07958-GM application, or SI5338A-B07958-GM equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL), independent per-output voltage control (1.5–3.3 V), sub-1 ps RMS jitter performance, PCIe Gen 4 common clock compliance, and I²C-based field reprogramming capability.

Technical Context

The SI5338A-B07958-GM implements a two-stage synthesis architecture: a PLL-based first stage (with 1.6 MHz loop bandwidth) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers enabling any-frequency generation on each output. Each MultiSynth supports integer or fractional mode with <1 ppb frequency resolution.

It features full I²C/SMBus programmability, loss-of-lock and loss-of-signal alarms, independent phase/frequency increment/decrement control (<20 ps step accuracy), and configurable spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation rate) on any output. External feedback mode enables zero-delay operation for clock distribution networks.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS)
Output Count & Type	4 independent outputs; supports LVPECL (0.16–710 MHz), LVDS (0.16–350 MHz), HCSL (0.16–250 MHz), CMOS (0.16–200 MHz), SSTL/HSTL (0.16–350 MHz)
Input Reference Options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3
Operating Temperature	–40 °C to +85 °C ambient; qualified per industrial temperature grade
Power Consumption	45 mA typical core current at 100 MHz on all outputs with 25 MHz reference

Pinout & Package

SI5338A-B07958-GM is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair #1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled
IN3, IN4	Single-ended input pair	Supports CMOS/SSTL/HSTL inputs (5–350 MHz); VIL = 0.3×VDD, VIH = 0.7×VDD
CLK0A, CLK0B – CLK3A, CLK3B	Differential output pairs	Four independent differential outputs; each configurable for LVPECL/LVDS/HCSL/CML format and voltage
VDDO0 – VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; decoupling required per bank
VDD	Core supply	Single 1.8/2.5/3.3 V supply for PLL, MultiSynth, and logic; PSRR optimized
SCL, SDA	I²C interface	Standard SMBus-compatible 100/400 kHz interface; supports write-only configuration and readback of status registers
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal condition

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent fractional-N synthesizers enable simultaneous generation of unrelated frequencies (e.g., 100 MHz PCIe + 125 MHz Ethernet + 156.25 MHz SerDes + 200 MHz processor clock) with true zero ppm accuracy
PCIe Gen 4 Common Clock Compliance	0.15–0.45 ps RMS jitter across 10 kHz–50 MHz band meets PCIe Base Spec 4.0 requirements for common clock architecture
Independent Output Voltage Control	Each of four output banks powered by dedicated VDDOx pins (1.5/1.8/2.5/3.3 V), eliminating level-shifting components in mixed-voltage systems
Glitchless Frequency Adjustment	Hardware-supported frequency increment/decrement via PINC/FDEC pins enables real-time, sub-ppm-step clock tuning without output interruption
Programmable Phase Offset	±45 ns initial phase offset per output with <20 ps step resolution, enabling precise skew management across multi-lane interfaces (e.g., DDR, PCIe)
Spread Spectrum Clocking (SSC)	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate, supporting EMI reduction without violating timing budgets

Applications

PCIe Root Complex Timing	Ethernet Switch Fabric Clocking
Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe endpoints and root ports in a server motherboard or network adapter. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks to PCIe Gen 3/4 receivers while supporting spread spectrum for EMI compliance. Use Value: Eliminates four discrete oscillators; achieves <0.45 ps RMS jitter required for PCIe Gen 4 link training; enables dynamic frequency margining via I²C.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and switch fabric ASICs in a modular line card. IC Role / Device Role / Timing Role: Configurable clock source supporting mixed-signal SoCs with varying voltage and format requirements (LVDS for PHYs, HCSL for SerDes, CMOS for control logic). Use Value: Single device replaces multiple oscillators and level shifters; independent VDDOx supplies allow direct interface to 1.2 V, 1.8 V, and 2.5 V domains without external regulators.
Broadcast Video Synchronization	FPGA-Based Test Equipment
Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI transceivers, video processors, and frame synchronizers in broadcast infrastructure. IC Role / Device Role / Timing Role: Precision clock generator with programmable phase offset and low deterministic jitter (<10 ps pk-pk cycle-cycle) for SMPTE ST 2082-1 timing compliance. Use Value: Sub-20 ps phase step resolution enables fine-grained skew alignment across multi-channel video paths; supports external feedback for zero-delay genlock loops.	Use Scenario: Supplying multiple precisely timed clocks (e.g., 100 MHz system clock, 200 MHz ADC sampling clock, 500 MHz DAC update clock) to FPGA-based instrumentation with tight setup/hold margins. IC Role / Device Role / Timing Role: Reconfigurable clock source enabling rapid prototyping of mixed-clock-domain test systems via ClockBuilder Pro GUI and I²C scripting. Use Value: Field-upgradable frequency plans eliminate hardware respins; independent MultiSynth outputs avoid inter-channel jitter coupling seen in shared-divider architectures.

PCIe Root Complex Timing

Ethernet Switch Fabric Clocking

Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe endpoints and root ports in a server motherboard or network adapter.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks to PCIe Gen 3/4 receivers while supporting spread spectrum for EMI compliance.

Use Value: Eliminates four discrete oscillators; achieves <0.45 ps RMS jitter required for PCIe Gen 4 link training; enables dynamic frequency margining via I²C.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and switch fabric ASICs in a modular line card.

IC Role / Device Role / Timing Role: Configurable clock source supporting mixed-signal SoCs with varying voltage and format requirements (LVDS for PHYs, HCSL for SerDes, CMOS for control logic).

Use Value: Single device replaces multiple oscillators and level shifters; independent VDDOx supplies allow direct interface to 1.2 V, 1.8 V, and 2.5 V domains without external regulators.

Broadcast Video Synchronization

FPGA-Based Test Equipment

Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI transceivers, video processors, and frame synchronizers in broadcast infrastructure.

IC Role / Device Role / Timing Role: Precision clock generator with programmable phase offset and low deterministic jitter (<10 ps pk-pk cycle-cycle) for SMPTE ST 2082-1 timing compliance.

Use Value: Sub-20 ps phase step resolution enables fine-grained skew alignment across multi-channel video paths; supports external feedback for zero-delay genlock loops.

Use Scenario: Supplying multiple precisely timed clocks (e.g., 100 MHz system clock, 200 MHz ADC sampling clock, 500 MHz DAC update clock) to FPGA-based instrumentation with tight setup/hold margins.

IC Role / Device Role / Timing Role: Reconfigurable clock source enabling rapid prototyping of mixed-clock-domain test systems via ClockBuilder Pro GUI and I²C scripting.

Use Value: Field-upgradable frequency plans eliminate hardware respins; independent MultiSynth outputs avoid inter-channel jitter coupling seen in shared-divider architectures.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D07958-GM	Higher integration: includes integrated crystal, lower power (32 mA typ), enhanced jitter (0.35 ps RMS), but limited to three outputs and no SSC support	Best suited for space-constrained, ultra-low-jitter applications where only three clocks are needed and EMI reduction is not required	Select when board area and jitter are prioritized over output count and spread spectrum capability
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS clock generator; 0.9 ps RMS jitter; no I²C interface or MultiSynth flexibility	Applicable only in stable, unchanging clock trees where field reconfiguration is unnecessary	Choose only for cost-sensitive, high-volume designs with static clock requirements and no need for firmware updates

Compared with Si5332A-D07958-GM and ICS8430I-01T, the SI5338A-B07958-GM uniquely balances field programmability, four independent outputs, PCIe Gen 4 compliance, and spread spectrum support-making it optimal for complex, evolving timing architectures requiring design flexibility and long-term maintainability.

Availability

SI5338A-B07958-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, 10 GbE switch fabric designs, and broadcast video timing systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338A-B07958-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, and Fibre Channel-enabling flexible, future-proof timing architectures in data center and telecom equipment.

FAQ

What is the primary function of the SI5338A-B07958-GM in a PCIe Gen 4 system?

The SI5338A-B07958-GM serves as the common clock source for PCIe Gen 4 root complexes and endpoints, delivering four low-jitter (≤0.45 ps RMS) synchronized clocks that meet the PCI-SIG Base Specification 4.0 jitter requirements. Its MultiSynth™ architecture ensures zero ppm frequency accuracy across all outputs, and its I²C programmability allows runtime adjustment of clock frequencies during link training or thermal compensation-critical for maintaining Gen 4 link stability under varying operating conditions. SI5338A-B07958-GM supports both common clock and separate reference no spread (SRNS) modes.

Does the SI5338A-B07958-GM support spread spectrum clocking (SSC), and how is it configured?

Yes, the SI5338A-B07958-GM supports fully configurable spread spectrum clocking on any individual output. SSC parameters-including spread percentage (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread only)-are programmed via I²C registers. The feature is implemented in the output stage and does not affect PLL stability or phase noise. Default settings are 0.5% down-spread at ~31.5 kHz. SI5338A-B07958-GM enables EMI reduction without compromising timing margins, and SSC can be enabled/disabled per output dynamically during operation.

Can the SI5338A-B07958-GM generate different output formats simultaneously (e.g., LVDS and HCSL)?

Yes, the SI5338A-B07958-GM supports mixed output formats across its four outputs. Each output driver (CLK0–CLK3) is independently configurable for LVPECL, LVDS, HCSL, CML, CMOS, SSTL, or HSTL-subject to frequency limits per format (e.g., LVPECL up to 710 MHz, HCSL up to 250 MHz). Format selection is register-controlled and requires appropriate VDDOx supply voltage (e.g., 2.5 V for LVDS, 1.8 V for HCSL). SI5338A-B07958-GM eliminates need for external level translators in heterogeneous timing systems.

What input reference options does the SI5338A-B07958-GM support, and are external components required?

The SI5338A-B07958-GM accepts six input reference types: crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz). For differential inputs (IN1/IN2, IN5/IN6), an external 100 Ω termination resistor is required. For crystal inputs, no external load capacitors are needed-the device integrates programmable on-chip capacitance (11–13 pF supported, 17–19 pF recommended). CMOS inputs require no external components beyond standard decoupling. SI5338A-B07958-GM provides automatic input detection and format adaptation.

How is the SI5338A-B07958-GM programmed, and is hardware configuration possible?

The SI5338A-B07958-GM is programmed exclusively via its I²C/SMBus interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software, which generates register configuration files and supports GUI-based frequency planning. No hardware strapping or OTP programming is available-the device boots from internal one-time-programmable (OTP) memory containing factory-default settings, but all runtime configurations are loaded via I²C. SI5338A-B07958-GM supports readback of status registers (e.g., lock status, LOS flag) and allows field updates without power cycling.

SI5338A-B07958-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B07958-GM FAQ

1.How can I place an order for SI5338A-B07958-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B07958-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B07958-GM reliable?

The price and inventory of SI5338A-B07958-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B07958-GM is usually 5 days.

3.What payment methods are accepted for SI5338A-B07958-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B07958-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B07958-GM?

SI5338A-B07958-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B07958-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B07958-GM?

For technical support, including SI5338A-B07958-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B07958-GM requirements.

6.How does Aetrix verify that SI5338A-B07958-GM is sourced from the original manufacturer or authorized distributors?

All SI5338A-B07958-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B07958-GM meets industry standards.

7.What is the process for return or replacement of SI5338A-B07958-GM?

All SI5338A-B07958-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B07958-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B07958-GM part is unused and in its original packaging.

Return procedure for SI5338A-B07958-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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