Skyworks Solutions Inc. SI5338A-B08772-GMR
- Part No.:
- SI5338A-B08772-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338A-B08772-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:2,053
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338A-B08772-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.
For engineers reviewing the SI5338A-B08772-GMR datasheet, SI5338A-B08772-GMR pinout, SI5338A-B08772-GMR application, or SI5338A-B08772-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), low-power 4×4 mm QFN package, and I²C/SMBus programmability with ClockBuilder Pro support.
Technical Context
The SI5338A-B08772-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) feeding a fractional-N MultiSynth™ synthesis stage per output. Each of the four outputs supports independent frequency, format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), and voltage configuration.
It features real-time glitchless frequency adjustment in 1 ppm steps, <20 ps phase step resolution, spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate), loss-of-lock and loss-of-signal alarms, and zero-delay mode via external feedback - all controlled through a 400 kHz I²C interface with OTP NVM storage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Count & Type | 4 independent outputs; configurable as differential (LVPECL/LVDS/HCSL/CML) or single-ended (CMOS/SSTL/HSTL) |
| Frequency Range | 0.16–710 MHz per output; supports integer/fractional synthesis with 1 ppb resolution |
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 Common Clock specs |
| Supply Voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V |
| Input Flexibility | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating Temp | –40 to +85 °C ambient; qualified for industrial and telecom line card environments |
Pinout & Package
SI5338A-B08772-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential reference input pair | Accepts 5–710 MHz AC-coupled differential clocks; internal 100 Ω termination enabled |
| IN3, IN4 | Single-ended reference inputs | Support CMOS/SSTL/HSTL signals (5–350 MHz); each independently selectable as primary ref |
| CLK0A/CLK0B–CLK3A/CLK3B | Differential output pairs | Four fully independent outputs; each configurable for format, frequency, voltage, and enable |
| VDDO0–VDDO3 | Per-output buffer supply pins | Enable independent voltage setting (1.5/1.8/2.5/3.3 V) per output driver |
| SCL, SDA | I²C serial interface | 400 kHz max; supports standard SMBus protocol and ClockBuilder Pro programming |
| INTR | Interrupt output | Open-drain status pin indicating loss-of-lock, loss-of-signal, or configuration error |
| VDD | Core supply | Single 1.8/2.5/3.3 V supply; PSRR optimized for clean core operation |
| GND, RSVD_GND | Ground connections | Multiple GND pins and reserved ground pad ensure low-noise return path and thermal dissipation |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Any-Frequency Synthesis | Generates four independent, zero-ppm-accurate output frequencies from one reference, eliminating multiple XO dependencies |
| PCIe Gen 1–4 Compliance | Fully satisfies Common Clock jitter requirements (Gen 1–4) and Gen 3 Separate Reference No Spread (SRNS) spec |
| Independent Output Voltage Control | Each output driver powered from dedicated VDDOx pin, enabling mixed-voltage system clocking without level shifters |
| Glitchless Frequency Adjustment | Real-time ±1 ppm step tuning via PINC/FDEC pins or I²C, preserving signal continuity during dynamic reconfiguration |
| Programmable Phase Offset | ±45 ns fine phase alignment per output with <20 ps step resolution for timing-critical skew management |
| Spread Spectrum Support | Configurable SSC on any output (0.5–5.0% spread, 33–63 kHz rate) to reduce EMI in dense PCB layouts |
Applications
| Ethernet Switch/Router Timing | PCIe Gen 1–4 Clocking |
|---|---|
Use Scenario: High-port-count Layer 3 switches requiring synchronized 125 MHz, 156.25 MHz, and 312.5 MHz clocks for SerDes lanes and packet processing logic. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent, low-jitter clocks to PHY, MAC, and CPU subsystems. Use Value: Eliminates four discrete oscillators; enables per-lane frequency margining and phase alignment to meet IEEE 802.3bj jitter budgets. |
Use Scenario: Server motherboard with multiple PCIe Gen 4 x16 slots, requiring compliant common-clock distribution with <0.45 ps RMS jitter. IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering 100 MHz HCSL clocks to root complex and endpoint devices. Use Value: Meets PCIe Gen 4 Common Clock spec (0.15–0.45 ps RMS) without external jitter cleaners; supports spread spectrum for EMI reduction. |
| Processor & FPGA Clocking | Broadcast Video/Audio Timing |
Use Scenario: Heterogeneous SoC platform with ARM cores, GPU, DDR4 memory, and FPGA fabric, each demanding distinct clock domains (e.g., 500 MHz, 300 MHz, 200 MHz). IC Role / Device Role / Timing Role: Configurable multi-frequency clock source generating synchronous and asynchronous clocks from a single 25 MHz crystal. Use Value: Reduces BOM count and board area vs. discrete oscillators; supports dynamic voltage/frequency scaling (DVFS) via I²C reprogramming. |
Use Scenario: SMPTE ST 2082 (12G-SDI) video router requiring ultra-low-jitter 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks for encoder/decoder synchronization. IC Role / Device Role / Timing Role: Precision clock synthesizer delivering sub-1 ps RMS jitter outputs traceable to master studio reference. Use Value: Achieves broadcast-grade timing stability (<10 ps pk-pk period jitter) without oven-controlled oscillators; supports frame-accurate genlock. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D08772-GM | Higher integration: includes integrated LDOs, enhanced jitter performance (0.35 ps RMS), and higher max output frequency (1.4 GHz) | Targets next-gen PCIe Gen 5, CXL, and 800G optical modules where tighter jitter and wider bandwidth are required | Select when upgrading beyond Gen 4 PCIe or needing >710 MHz outputs; requires revised power design due to integrated LDOs |
| ICS843002AGI-01LFT | Fixed-frequency, non-programmable quad LVDS generator; no I²C interface or MultiSynth™ flexibility | Used in cost-sensitive, static-clocking applications like legacy telecom line cards with unchanging frequency plans | Choose only for fixed-frequency deployments where programmability adds no value; lacks PCIe SRNS compliance and spread spectrum |
Compared with Si5332A-D08772-GM, SI5338A-B08772-GMR offers broader input flexibility and lower system cost for Gen 4 applications; compared with ICS843002AGI-01LFT, it provides field-reprogrammability and PCIe compliance at the expense of higher design complexity.
Availability
SI5338A-B08772-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 add-in cards, and FPGA-based video processing systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338A-B08772-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed digital systems including PCIe, Ethernet, and broadcast infrastructure - designed to replace multiple discrete oscillators with a single programmable IC.
FAQ
What is the maximum output frequency supported by SI5338A-B08772-GMR?
The SI5338A-B08772-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) per the device's synthesis architecture.
Does SI5338A-B08772-GMR support PCIe Gen 4 Common Clock compliance?
Yes, SI5338A-B08772-GMR meets PCIe Gen 4 Common Clock jitter requirements with ≤0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks' recommended settings, including PLL bandwidth of 2–5 MHz and use of differential HCSL outputs.
Can SI5338A-B08772-GMR generate different output voltages on each channel?
Yes - SI5338A-B08772-GMR provides independent VDDO0–VDDO3 pins, allowing each of its four outputs to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage ASICs, FPGAs, and SerDes without external level shifters.
How is SI5338A-B08772-GMR programmed, and is firmware required?
SI5338A-B08772-GMR is programmed via I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which generates configuration files written to on-chip OTP memory. No external microcontroller or runtime firmware is needed - the device boots preconfigured.
What package type and footprint does SI5338A-B08772-GMR use?
SI5338A-B08772-GMR uses a 24-lead QFN package measuring 4 × 4 mm with 0.5 mm pitch and an exposed thermal pad. The pinout matches the standard Si5338 family layout, and Skyworks provides recommended land patterns and solder stencil guidelines in the datasheet.
SI5338A-B08772-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338A-B08772-GMR FAQ
1.How can I place an order for SI5338A-B08772-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338A-B08772-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338A-B08772-GMR reliable?
The price and inventory of SI5338A-B08772-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B08772-GMR is usually 5 days.
3.What payment methods are accepted for SI5338A-B08772-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B08772-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338A-B08772-GMR?
SI5338A-B08772-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338A-B08772-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338A-B08772-GMR?
For technical support, including SI5338A-B08772-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B08772-GMR requirements.
6.How does Aetrix verify that SI5338A-B08772-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338A-B08772-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B08772-GMR meets industry standards.
7.What is the process for return or replacement of SI5338A-B08772-GMR?
All SI5338A-B08772-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B08772-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338A-B08772-GMR part is unused and in its original packaging.
Return procedure for SI5338A-B08772-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338A-B08772-GMR Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

