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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B08985-GM

Name: SI5338A-B08985-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B08985-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B08985-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338A-B08985-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338A-B08985-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338A-B08985-GM datasheet, SI5338A-B08985-GM pinout, SI5338A-B08985-GM application, or SI5338A-B08985-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage per driver (1.5–3.3 V), programmable phase/frequency increment (±45 ns / 20 ps step), spread-spectrum capability (0.5–5.0% spread), and 24-QFN package with 4×4 mm footprint.

Technical Context

The SI5338A-B08985-GM implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) feeding a fractional-N MultiSynth™ synthesizer per output channel. Each of the four synthesis paths supports integer or fractional mode, enabling true zero-ppm frequency accuracy across all outputs.

Its output stage provides independent configuration per driver for signal format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), output voltage (1.5/1.8/2.5/3.3 V), and termination control. The device supports both free-running generation and synchronous frequency translation modes, with loss-of-lock and loss-of-signal alarms for system monitoring.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and 10 GbE jitter requirements
Output Frequency Range	0.16–710 MHz - covers PCIe, Ethernet, Fibre Channel, and broadcast video rates
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), differential (5–710 MHz) - enables flexible system clock sourcing
Output Formats	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - supports mixed-technology board-level clock distribution
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.4–3.63 V - allows independent IO voltage per output bank
Package	24-pin QFN, 4 × 4 mm - space-efficient for dense FPGA/ASIC timing layouts
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments

Pinout & Package

SI5338A-B08985-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: pins 1–24 include six clock inputs (IN1–IN6), eight differential output pairs (CLK0A/B through CLK3A/B), four VDDO supplies (VDDO0–VDDO3), dual-core VDD, SCL/SDA/I²C interface, INTR alarm output, and reserved ground.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled 5–710 MHz differential references; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support DC-coupled CMOS/SSTL/HSTL inputs up to 350 MHz; VIH/VIL referenced to VDD
CLK0A–CLK3B	Differential output pairs	Four independent output banks; each pair configurable for LVPECL/LVDS/HCSL/CML with dedicated VDDO
VDDO0–VDDO3	Output buffer supply rails	Enable per-output voltage setting (1.5/1.8/2.5/3.3 V) to match connected IC logic families
SCL, SDA	I²C serial interface	SMBus-compatible 100/400 kHz control bus; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status pin asserting on loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis per output	Enables independent, any-frequency generation (0.16–710 MHz) with 0 ppm error-no external crystals needed
Independent output voltage control	Each of four output banks powered by separate VDDO rail (1.5/1.8/2.5/3.3 V), eliminating level-shifter components
Programmable phase adjustment	±45 ns range in <20 ps steps per output-enables precise skew alignment across multi-lane interfaces like PCIe or DDR
Glitchless frequency tuning	1 ppm incremental/decremental frequency change via PINC/FDEC pins-supports dynamic rate adaptation without clock interruption
Spread-spectrum clocking	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output-reduces EMI peak emissions in noise-sensitive systems

Applications

PCIe Gen 3/4 Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz common clock and 100 MHz SRNS reference to multiple PCIe Gen 3/4 root complexes and endpoints on a server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter (<0.32 ps RMS) PCIe-compliant clocks with independent phase alignment per lane group. Use Value: Eliminates need for four discrete oscillators while meeting PCIe Gen 4 jitter mask and enabling per-lane deskew via programmable phase offsets.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet buffers in a Layer 3 switch ASIC design. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact Ethernet line rates with sub-ps jitter and independent voltage control per PHY interface. Use Value: Reduces BOM count and layout area versus discrete XO + buffer solutions; supports mixed-voltage PHYs (1.8 V/2.5 V/3.3 V) from one IC.
Broadcast Video Sync	FPGA/ASIC Reference Clocking
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock (270 MHz), genlock reference (27 MHz), and audio sample clock (48 kHz) to a 4K/8K video processing platform. IC Role / Device Role / Timing Role: Multi-format clock generator supporting LVDS, HCSL, and CMOS outputs simultaneously at precise broadcast frequencies. Use Value: Achieves <10 ps cycle-cycle jitter required for uncompressed video transport; eliminates timing skew between video/audio domains via correlated phase offsets.	Use Scenario: Supplying 300 MHz system clock, 150 MHz DDR4 memory clock, 200 MHz transceiver reference, and 100 MHz debug clock to a Xilinx Versal ACAP. IC Role / Device Role / Timing Role: Configurable quad clock source with independent output formats (LVDS for memory, HCSL for GTY, CMOS for peripherals) and voltage rails. Use Value: Replaces three separate clock ICs; enables dynamic reconfiguration of FPGA clock trees via I²C during runtime or boot.

PCIe Gen 3/4 Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz common clock and 100 MHz SRNS reference to multiple PCIe Gen 3/4 root complexes and endpoints on a server motherboard.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter (<0.32 ps RMS) PCIe-compliant clocks with independent phase alignment per lane group.

Use Value: Eliminates need for four discrete oscillators while meeting PCIe Gen 4 jitter mask and enabling per-lane deskew via programmable phase offsets.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet buffers in a Layer 3 switch ASIC design.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact Ethernet line rates with sub-ps jitter and independent voltage control per PHY interface.

Use Value: Reduces BOM count and layout area versus discrete XO + buffer solutions; supports mixed-voltage PHYs (1.8 V/2.5 V/3.3 V) from one IC.

Broadcast Video Sync

FPGA/ASIC Reference Clocking

Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock (270 MHz), genlock reference (27 MHz), and audio sample clock (48 kHz) to a 4K/8K video processing platform.

IC Role / Device Role / Timing Role: Multi-format clock generator supporting LVDS, HCSL, and CMOS outputs simultaneously at precise broadcast frequencies.

Use Value: Achieves <10 ps cycle-cycle jitter required for uncompressed video transport; eliminates timing skew between video/audio domains via correlated phase offsets.

Use Scenario: Supplying 300 MHz system clock, 150 MHz DDR4 memory clock, 200 MHz transceiver reference, and 100 MHz debug clock to a Xilinx Versal ACAP.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent output formats (LVDS for memory, HCSL for GTY, CMOS for peripherals) and voltage rails.

Use Value: Replaces three separate clock ICs; enables dynamic reconfiguration of FPGA clock trees via I²C during runtime or boot.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08985-GM	Higher integration: integrated crystal, lower power (32 mA typ), improved jitter (0.35 ps RMS), supports up to 10 outputs	Targeted at newer designs requiring higher channel count and tighter jitter budgets; lacks direct pin compatibility	Select when upgrading from Si5338A for next-gen PCIe 5.0 or 400G Ethernet; requires PCB redesign due to different pinout and package (32-QFN)
ICS853S02IAGLF	Fixed-frequency, non-programmable quad LVDS clock generator; no I²C interface; 1.2 ps RMS jitter; 32-pin TSSOP	Only suitable where fixed frequencies are acceptable; no frequency translation or phase tuning capability	Choose only for cost-sensitive, static-clock applications with no requirement for reconfiguration or spread spectrum

Compared with Si5332A-D08985-GM and ICS853S02IAGLF, the SI5338A-B08985-GM uniquely balances field-programmability, PCIe Gen 4 compliance, and 24-QFN compactness-making it optimal for mid-life-cycle upgrades and mixed-signal timing consolidation where flexibility and proven qualification matter more than lowest jitter or highest channel count.

Availability

SI5338A-B08985-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, 10 GbE switch/router clocking, and broadcast video synchronization requiring stable component supply and long-term industrial availability.

Supply support for SI5338A-B08985-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog ICs for communications, automotive, and industrial markets.

The Si5338 product line was designed specifically for high-performance, software-configurable clock generation in data center, networking, and broadcast infrastructure-emphasizing low jitter, multi-format flexibility, and I²C-based field reprogrammability.

FAQ

What is the maximum output frequency supported by SI5338A-B08985-GM?

The SI5338A-B08985-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS outputs. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) due to internal VCO constraints. All outputs maintain 0.7 ps RMS typical phase jitter within their respective rated ranges.

Does SI5338A-B08985-GM support PCIe Gen 4 Common Clock compliance?

Yes, SI5338A-B08985-GM is compliant with PCIe Gen 4 Common Clock specifications, delivering ≤0.45 ps RMS jitter (10 kHz–50 MHz) under specified test conditions (100 MHz HCSL outputs, PLL BW 2–4 MHz, CDR = 10 MHz). This compliance is verified per PCI-SIG Base Specification 4.0 rev. 0.5 and confirmed using the Skyworks PCIe Clock Jitter Tool.

Can SI5338A-B08985-GM generate different output voltages on each of its four output banks?

Yes, SI5338A-B08985-GM supports independent output supply rails (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous driving of mixed-logic-family devices-e.g., 1.8 V FPGA transceivers, 2.5 V Ethernet PHYs, and 3.3 V microcontrollers-without external level shifters or discrete regulators.

How is SI5338A-B08985-GM programmed, and what tools are required?

SI5338A-B08985-GM is programmed via its I²C/SMBus-compatible interface using Skyworks' ClockBuilder Pro software. The tool enables full register configuration, frequency synthesis setup, spread-spectrum parameters, and phase offset definition. Configuration can be stored in on-chip OTP memory for autonomous startup, or loaded dynamically at runtime via host processor.

What input reference options does SI5338A-B08985-GM support?

SI5338A-B08985-GM accepts multiple reference sources: an 8–30 MHz fundamental-mode crystal (internally buffered), single-ended CMOS inputs (5–200 MHz), differential inputs (5–710 MHz), or SSTL/HSTL inputs (5–350 MHz). Input selection is configurable per channel, allowing hybrid reference architectures-for example, crystal for primary stability and external clock for failover or synchronization.

SI5338A-B08985-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Obsolete

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338A-B08985-GM FAQ

1.How can I place an order for SI5338A-B08985-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B08985-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B08985-GM reliable?

The price and inventory of SI5338A-B08985-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B08985-GM is usually 5 days.

3.What payment methods are accepted for SI5338A-B08985-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B08985-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B08985-GM?

SI5338A-B08985-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B08985-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B08985-GM?

For technical support, including SI5338A-B08985-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B08985-GM requirements.

6.How does Aetrix verify that SI5338A-B08985-GM is sourced from the original manufacturer or authorized distributors?

All SI5338A-B08985-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B08985-GM meets industry standards.

7.What is the process for return or replacement of SI5338A-B08985-GM?

All SI5338A-B08985-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B08985-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B08985-GM part is unused and in its original packaging.

Return procedure for SI5338A-B08985-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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