Skyworks Solutions Inc. SI5338A-B08985-GMR

Overview

SI5338A-B08985-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router and FPGA clocking systems.

For engineers reviewing the SI5338A-B08985-GMR datasheet, SI5338A-B08985-GMR pinout, SI5338A-B08985-GMR application, or SI5338A-B08985-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338A-B08985-GMR implements a two-stage PLL architecture: a high-performance integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each MultiSynth supports frequency resolution down to 1 ppb and programmable phase offset (±45 ns, <20 ps step).

It features full input flexibility - external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) - and output configurability per driver: LVPECL/LVDS (0.16–710 MHz), HCSL (0.16–250 MHz), CMOS (0.16–200 MHz), or SSTL/HSTL (0.16–350 MHz), with independent VDDO supply per output bank.

Key Specifications

Pinout & Package

SI5338A-B08985-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet Section 7 and Figure 1 (Top View).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338A-B08984-GM, SI5338A-B08985-GMR offers field-programmable flexibility via I²C, while LMK04832RHAR trades compact size and SSC for lower jitter and greater output count - making SI5338A-B08985-GMR optimal for space-constrained, multi-protocol systems needing rapid reconfiguration.

Availability

SI5338A-B08985-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 4 clock distribution, and broadcast video synchronization requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338A-B08985-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with >30 years of RF and clocking expertise.

The Si5338 product line was designed for high-density, multi-protocol systems requiring flexible, low-jitter clock generation - specifically targeting networking, data center, broadcast, and FPGA-based platforms where board space, power, and timing precision are critical.

FAQ

What is the default factory configuration of the SI5338A-B08985-GMR?

The SI5338A-B08985-GMR ships with non-volatile memory (NVM) pre-programmed for a specific frequency plan, typically configured for a 25 MHz crystal input and four common output frequencies (e.g., 100 MHz, 125 MHz, 156.25 MHz, 312.5 MHz). Configuration can be fully overwritten via I²C using ClockBuilder Pro software. SI5338A-B08985-GMR retains user-defined settings after power cycle unless explicitly erased.

Does the SI5338A-B08985-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338A-B08985-GMR supports PCIe Gen 4 SRNS mode with ≤0.32 ps RMS jitter (typical) when configured with a PLL bandwidth of 2–4 MHz and CDR = 10 MHz. This mode is enabled via register settings and validated per PCI-SIG Base Specification 4.0 rev. 0.5. SI5338A-B08985-GMR achieves this using its independent MultiSynth™ stage with optimized loop filter coefficients.

Can the SI5338A-B08985-GMR generate four different frequencies simultaneously above 350 MHz?

No - the SI5338A-B08985-GMR can output only two unique frequencies above 350 MHz simultaneously (Fvco/4 and Fvco/6), as constrained by its VCO architecture. All four outputs may operate above 350 MHz only if two share one frequency and the other two share another. For example: CLK0A/B = 473.33 MHz, CLK1A/B = 473.33 MHz, CLK2A/B = 710 MHz, CLK3A/B = 710 MHz. SI5338A-B08985-GMR's datasheet Section 3.3 confirms this limitation.

What is the minimum input slew rate required for low-jitter operation of the SI5338A-B08985-GMR?

For optimal jitter performance, the SI5338A-B08985-GMR requires ≥0.3 V/ns midpoint differential input slew rate on IN1/IN2 and IN5/IN6, and ≥1.0 V/ns midpoint single-ended slew rate on IN3/IN4. These values are specified in Table 6 Notes 2 and 4 of the Rev. 1.6 datasheet and directly impact measured phase jitter - falling below them increases deterministic jitter components in SI5338A-B08985-GMR outputs.

How does the SI5338A-B08985-GMR handle loss-of-signal (LOS) detection?

The SI5338A-B08985-GMR monitors all six input pins (IN1–IN6) for LOS with detection time of 2.6–5 µs and release time of 0.01–1 µs. When triggered, it asserts the open-drain INTR pin and updates internal status registers. LOS detection remains active in both PLL and bypass modes, though minimum input frequency drops to 1 MHz in bypass (with reduced LOS reliability). SI5338A-B08985-GMR provides separate LOS flags per input in register 0x001D.