Skyworks Solutions Inc. SI5338A-B09174-GM
- Part No.:
- SI5338A-B09174-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- -
- Datasheet:
-
SI5338A-B09174-GM.pdf
- Description:
- IC CLOCK GENERATOR QUAD 24QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338A-B09174-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338A-B09174-GM datasheet, SI5338A-B09174-GM pinout, SI5338A-B09174-GM application, or SI5338A-B09174-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% down-spread), and loss-of-lock/loss-of-signal alarm support.
Technical Context
The SI5338A-B09174-GM implements a two-stage PLL architecture: a high-stability reference stage (input frequency 5–710 MHz) followed by four independent MultiSynth™ synthesis blocks, each supporting integer or fractional-N division with programmable R, M, and P dividers. Each output path includes configurable format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent VDDO supply, and fine-grained phase/frequency adjustment (±45 ns range, 20 ps step).
It supports external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references, and enables zero-delay mode via external feedback. The device integrates OTP NVM for factory programming and features I²C/SMBus-compatible serial control with interrupt (INTR) signaling for status monitoring.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock spec (≤0.45 ps RMS) |
| Output Count & Type | 4 differential outputs (CLK0A/B–CLK3A/B); supports up to 8 single-ended or mixed configurations |
| Frequency Range | 0.16–710 MHz per output; LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V |
| Operating Temperature | –40 °C to +85 °C; qualified for industrial embedded and telecom line card environments |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, exposed thermal pad |
Pinout & Package
SI5338A-B09174-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential input pair 1 | Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination option |
| IN3, IN4 | Single-ended input pair | Supports CMOS/SSTL/HSTL inputs (5–350 MHz); 0.7×VDD VIH threshold |
| IN5, IN6 | Differential input pair 2 | Second 5–710 MHz differential reference; enables dual-reference redundancy or translation |
| CLK0A, CLK0B – CLK3A, CLK3B | Differential output pairs | Four independent LVPECL/LVDS/HCSL/CML outputs; each with dedicated VDDOx supply |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5/1.8/2.5/3.3 V bias per output bank; enables mixed-voltage system interfacing |
| VDD | Core supply | Single 1.8/2.5/3.3 V supply for PLL, logic, and memory; 45 mA typical current at 100 MHz outputs |
| SCL, SDA | I²C interface | Standard SMBus-compatible 100/400 kHz control bus; supports register read/write and OTP programming |
| INTR | Interrupt output | Open-drain status flag for loss-of-lock, loss-of-signal, or configuration error events |
| RSVD_GND | Reserved ground | Internal test pin; must be connected to GND per layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs simultaneously |
| PCIe Gen 4 compliance | Validated 0.15–0.45 ps RMS jitter in Common Clock mode; supports SRNS for Gen 3 |
| Independent output control | Per-output format (LVPECL/LVDS/HCSL/CMOS), voltage (1.5–3.3 V), enable, and spread-spectrum modulation |
| Glitchless frequency tuning | 1 ppm step size via PINC/FDEC pins or I²C; update time ≤667 ns above 18 MHz |
| Programmable phase offset | ±45 ns range in 20 ps steps; enables precise skew alignment across multi-lane interfaces |
| Flexible reference options | Crystal (8–30 MHz), single-ended (5–350 MHz), or differential (5–710 MHz) inputs with automatic detection |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter clocks with matched phase alignment and spread-spectrum support to meet PCIe EMI requirements. Use Value: Eliminates need for four discrete oscillators; reduces board area by 65% and ensures <0.45 ps RMS jitter compliance across all lanes. |
Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and SerDes in enterprise switches. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer with independent output formatting (LVDS for PHYs, CMOS for controllers) and voltage scaling (1.8 V/2.5 V). Use Value: Enables single-device timing for heterogeneous Ethernet subsystems while maintaining <1 ps RMS jitter for BER <10⁻¹². |
| Broadcast Video Timing | FPGA/Processor Clocking |
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) reference clocks and genlock signals to video encoder/decoder FPGAs in 4K/8K broadcast infrastructure. IC Role / Device Role / Timing Role: High-precision clock generator with sub-20 ps phase step resolution and deterministic jitter <10 ps pk-pk for frame-accurate synchronization. Use Value: Supports exact-frequency synthesis of 270 MHz, 540 MHz, and 1.08 GHz clocks from a single 27 MHz crystal, eliminating timing drift between processing stages. |
Use Scenario: Supplying core, DDR, and peripheral clocks to Xilinx Versal or Intel Agilex FPGAs in AI inference accelerators. IC Role / Device Role / Timing Role: Configurable quad clock source with independent VDDO per output to drive FPGA banks requiring 1.2 V (core), 1.8 V (DDR), and 3.3 V (I/O) clock domains. Use Value: Reduces BOM count by consolidating clock trees; enables dynamic frequency scaling via I²C during runtime reconfiguration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D08189-GM | Higher integration: 8 outputs, integrated jitter cleaner, lower 0.35 ps RMS jitter; requires external 100 MHz reference for optimal performance | Targeted at ultra-low-jitter 100G/400G optical modules and coherent DSP timing where sub-0.4 ps RMS is mandatory | Select when >4 outputs or <0.4 ps RMS jitter is required; not drop-in due to different pinout and higher power (75 mA) |
| ICS8430I-01LG | Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; no spread spectrum or phase adjustment | Suitable for cost-sensitive, static-clocking applications like legacy storage controllers where frequency flexibility is unnecessary | Choose only for non-programmable, high-volume applications with fixed 100/125/156.25 MHz outputs; lacks PCIe Gen 4 validation and MultiSynth™ precision |
Compared with Si5332A-D08189-GM and ICS8430I-01LG, the SI5338A-B09174-GM delivers optimal balance of programmability, PCIe Gen 4 compliance, and industrial temperature support in a compact 24-QFN footprint-making it ideal for field-upgradable timing in networking and compute platforms where design reuse and future-proofing matter.
Availability
SI5338A-B09174-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and broadcast video timing applications requiring stable component supply, long-term lifecycle assurance, and full traceability.
Supply support for SI5338A-B09174-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The Si5338 product line was designed specifically for high-performance, programmable clock generation in data center, telecom, and broadcast systems-enabling consolidation of multiple oscillators into a single, software-configurable IC with industry-leading jitter performance.
FAQ
What is the maximum output frequency supported by SI5338A-B09174-GM in LVPECL mode?
The SI5338A-B09174-GM supports up to 710 MHz in LVPECL mode per output. This capability is confirmed in Table 6 of the datasheet under "Output Clocks (Differential)" for LVPECL/LVDS/CML formats. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6), and requires proper termination and layout per Skyworks AN562.
Does SI5338A-B09174-GM support PCIe Gen 4 Common Clock compliance out of the box?
Yes, SI5338A-B09174-GM is explicitly validated for PCIe Gen 4 Common Clock compliance with 0.15–0.45 ps RMS jitter (Table 12), meeting the PCI-SIG Base Specification 4.0 rev. 0.5. This performance is achieved using a 2–4 MHz PLL bandwidth and 10 MHz CDR, and is verified using the Skyworks PCIe Clock Jitter Tool.
Can SI5338A-B09174-GM generate four different output frequencies simultaneously?
Yes, SI5338A-B09174-GM can synthesize four independent frequencies simultaneously-each with zero-ppm precision-using its four dedicated MultiSynth™ blocks. Each output supports independent configuration of frequency, format, voltage, and spread-spectrum parameters without mutual interference.
What reference inputs does SI5338A-B09174-GM accept?
SI5338A-B09174-GM accepts six reference inputs: two differential pairs (IN1/IN2, IN5/IN6) for 5–710 MHz; two single-ended pins (IN3, IN4) for CMOS/SSTL/HSTL signals (5–350 MHz); and an internal crystal oscillator supporting 8–30 MHz crystals. All inputs are automatically detected and routed to the synthesis engine.
Is SI5338A-B09174-GM pin-compatible with other Si5338 variants?
Yes, all Si5338 variants-including SI5338A-B09174-GM-share identical 24-QFN pinout, footprint, and thermal pad layout per Skyworks Package Outline document #99-8Q-0014. This allows direct substitution within the same temperature grade (–40 to +85 °C) and package type without PCB changes.
SI5338A-B09174-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- -
SI5338A-B09174-GM FAQ
1.How can I place an order for SI5338A-B09174-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338A-B09174-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338A-B09174-GM reliable?
The price and inventory of SI5338A-B09174-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B09174-GM is usually 5 days.
3.What payment methods are accepted for SI5338A-B09174-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B09174-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338A-B09174-GM?
SI5338A-B09174-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338A-B09174-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338A-B09174-GM?
For technical support, including SI5338A-B09174-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B09174-GM requirements.
6.How does Aetrix verify that SI5338A-B09174-GM is sourced from the original manufacturer or authorized distributors?
All SI5338A-B09174-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B09174-GM meets industry standards.
7.What is the process for return or replacement of SI5338A-B09174-GM?
All SI5338A-B09174-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B09174-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338A-B09174-GM part is unused and in its original packaging.
Return procedure for SI5338A-B09174-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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