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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B09344-GMR

Name: SI5338A-B09344-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B09344-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B09344-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338A-B09344-GMR.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

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Product details

Overview

SI5338A-B09344-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338A-B09344-GMR datasheet, SI5338A-B09344-GMR pinout, SI5338A-B09344-GMR application, or SI5338A-B09344-GMR equivalent, key selection criteria include differential output jitter performance at 125 MHz (0.7 ps RMS), PCIe Gen 4 common clock compliance, independent per-output voltage control (1.5/1.8/2.5/3.3 V), 24-pin 4×4 mm QFN package, and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338A-B09344-GMR implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to an external crystal (8–30 MHz) or clock input (5–710 MHz), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each synthesizer supports integer or fractional mode operation with <20 ps programmable phase step resolution and 1 ppm frequency increment/decrement capability.

Output drivers are fully configurable per channel: format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), supply voltage (1.5–3.3 V), termination, and spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate). The device includes loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and operates across –40 to +85 °C with core supply options of 1.8/2.5/3.3 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); enables PCIe Gen 4 and 10 GbE timing compliance
Output Frequency Range	0.16–710 MHz per channel; supports simultaneous generation of PCIe 100 MHz, Ethernet 125 MHz, and processor 500 MHz clocks
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz); eliminates need for multiple reference sources
Output Format Flexibility	LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL per channel; allows direct interfacing to FPGAs, ASICs, and SerDes without level-shifting buffers
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver; simplifies mixed-voltage system design
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; space-efficient footprint compatible with high-density PCB layouts
Operating Temperature	–40 to +85 °C; qualified for industrial and telecom line card environments

Pinout & Package

SI5338A-B09344-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 pinout: dual differential inputs (IN1/IN2, IN5/IN6), two single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), six VDDOx supplies (VDDO0–VDDO3), core VDD, I²C interface (SCL/SDA), interrupt (INTR), and reserved ground (RSVD_GND).

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3 / IN4	Single-ended reference inputs	Support 5–200 MHz CMOS-level clocks; internally biased; no external termination required
CLK0A / CLK0B	Differential output pair 0	Configurable format/voltage; supports LVPECL/LVDS/HCSL/CML; driven by MultiSynth 0
CLK1A / CLK1B	Differential output pair 1	Independent frequency/format/voltage control; driven by MultiSynth 1
CLK2A / CLK2B	Differential output pair 2	Programmable phase offset (<20 ps steps); driven by MultiSynth 2
CLK3A / CLK3B	Differential output pair 3	Supports spread-spectrum modulation; driven by MultiSynth 3
VDDO0–VDDO3	Output buffer supply pins	Each powers one output pair; enables per-channel voltage selection (1.5–3.3 V)
SCL / SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports ClockBuilder Pro configuration and runtime reprogramming
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis per output	Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs without shared dividers
PCIe Gen 4 Common Clock compliance	0.15–0.45 ps RMS jitter (10 kHz–50 MHz) meets PCIe Base Spec 4.0 rev 0.5 requirements for 100 MHz HCSL outputs
Per-output voltage and format control	Each of four output pairs supports independent selection of 1.5/1.8/2.5/3.3 V supply and LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL signaling
Glitchless frequency adjustment	1 ppm step size with hardware pin control (FINC/FDEC) enables real-time frequency tuning without output interruption
Programmable spread spectrum	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI in noise-sensitive systems
External feedback mode	Enables zero-delay operation for clock distribution networks where input-to-output propagation delay must be minimized

Applications

PCIe Gen 4 Switch Timing	Ethernet 10GbE PHY Clocking
Use Scenario: High-bandwidth server switch ASIC requiring synchronized 100 MHz PCIe Gen 4 reference clocks across multiple lanes with strict jitter limits. IC Role / Device Role / Timing Role: Quad-output clock generator providing four independent 100 MHz HCSL clocks, each meeting PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS). Use Value: Eliminates four discrete oscillators; reduces board area by >60%; maintains sub-0.32 ps RMS jitter across temperature and voltage variation.	Use Scenario: 10GbE line card with dual 156.25 MHz PHY interfaces needing low-jitter, matched-phase clocks for SERDES alignment. IC Role / Device Role / Timing Role: Configurable clock source delivering two 156.25 MHz LVDS outputs with <100 ps inter-output skew and programmable phase offset. Use Value: Enables deterministic lane-to-lane skew control; supports IEEE 802.3ae jitter mask via 0.7 ps RMS phase noise performance.
FPGA-Based Broadcast Video Sync	Telecom Line Card Clock Translation
Use Scenario: Broadcast video processing FPGA requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with frame-sync phase alignment. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating three exact frequencies from a single 25 MHz crystal reference using integer-mode MultiSynth™. Use Value: Achieves zero-ppm frequency accuracy and <20 ps programmable phase steps for genlock-capable video timing.	Use Scenario: Telecom line card converting a 19.44 MHz SONET OC-12 reference into 155.52 MHz, 622.08 MHz, and 2488.32 MHz outputs for framer and DSP interfaces. IC Role / Device Role / Timing Role: Frequency translator with ultra-low additive jitter (0.165 ps RMS in buffer mode) preserving input reference integrity. Use Value: Maintains OC-12 jitter compliance (≤0.7 ps RMS) across all synthesized outputs without cascaded PLL degradation.

PCIe Gen 4 Switch Timing

Ethernet 10GbE PHY Clocking

Use Scenario: High-bandwidth server switch ASIC requiring synchronized 100 MHz PCIe Gen 4 reference clocks across multiple lanes with strict jitter limits.

IC Role / Device Role / Timing Role: Quad-output clock generator providing four independent 100 MHz HCSL clocks, each meeting PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS).

Use Value: Eliminates four discrete oscillators; reduces board area by >60%; maintains sub-0.32 ps RMS jitter across temperature and voltage variation.

Use Scenario: 10GbE line card with dual 156.25 MHz PHY interfaces needing low-jitter, matched-phase clocks for SERDES alignment.

IC Role / Device Role / Timing Role: Configurable clock source delivering two 156.25 MHz LVDS outputs with <100 ps inter-output skew and programmable phase offset.

Use Value: Enables deterministic lane-to-lane skew control; supports IEEE 802.3ae jitter mask via 0.7 ps RMS phase noise performance.

FPGA-Based Broadcast Video Sync

Telecom Line Card Clock Translation

Use Scenario: Broadcast video processing FPGA requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with frame-sync phase alignment.

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating three exact frequencies from a single 25 MHz crystal reference using integer-mode MultiSynth™.

Use Value: Achieves zero-ppm frequency accuracy and <20 ps programmable phase steps for genlock-capable video timing.

Use Scenario: Telecom line card converting a 19.44 MHz SONET OC-12 reference into 155.52 MHz, 622.08 MHz, and 2488.32 MHz outputs for framer and DSP interfaces.

IC Role / Device Role / Timing Role: Frequency translator with ultra-low additive jitter (0.165 ps RMS in buffer mode) preserving input reference integrity.

Use Value: Maintains OC-12 jitter compliance (≤0.7 ps RMS) across all synthesized outputs without cascaded PLL degradation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08789-GM	Higher integration: 8 outputs, integrated crystal option, lower jitter (0.35 ps RMS), but larger 32-QFN package	Better suited for multi-ASIC systems requiring >4 clocks; not drop-in compatible due to pin count and register map differences	Select when >4 outputs or sub-0.4 ps jitter is mandatory; requires PCB redesign and firmware update
ICS853S01IAGLF	Fixed-function 4-output LVDS clock generator; no I²C programming; 1.2 ps RMS jitter; 3.3 V only; 20-pin TSSOP	Limited to fixed 100/125/156.25 MHz outputs; no frequency or format flexibility; no spread spectrum	Choose for cost-sensitive, static-clock applications where programmability is unnecessary and jitter margin >0.5 ps is acceptable

Compared with Si5332A-D08789-GM and ICS853S01IAGLF, the SI5338A-B09344-GMR uniquely balances field-programmability, jitter performance, and compact 24-QFN packaging-making it optimal for PCIe Gen 4 and 10GbE designs requiring reconfigurable timing without layout changes.

Availability

SI5338A-B09344-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE PHY clocking, and FPGA-based broadcast video synchronization requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338A-B09344-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and precision timing expertise.

The Si5338 product line was designed for high-performance, multi-protocol serial interface timing-including PCIe, Ethernet, Fibre Channel, and broadcast video-where low jitter, flexible output configuration, and software-defined frequency synthesis are critical.

FAQ

What is the primary function of the SI5338A-B09344-GMR in a PCIe Gen 4 system?

The SI5338A-B09344-GMR serves as a quad-output common clock generator, delivering four synchronized 100 MHz HCSL clocks that meet PCIe Gen 4 SRNS jitter requirements (≤0.32 ps RMS). Its MultiSynth™ architecture ensures zero-ppm frequency accuracy and <100 ps inter-output skew, enabling reliable multi-lane link training and stable high-speed data transfer in switches and accelerators.

Does the SI5338A-B09344-GMR support spread-spectrum clocking (SSC), and how is it configured?

Yes, the SI5338A-B09344-GMR supports programmable spread-spectrum clocking on any output, with adjustable spread (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread only). Configuration is performed via I²C registers or ClockBuilder Pro software; no external components are required, and SSC can be enabled/disabled dynamically during operation.

Can the SI5338A-B09344-GMR generate different output voltages simultaneously on its four channels?

Yes, the SI5338A-B09344-GMR supports independent output buffer supply voltages per channel: VDDO0 powers CLK0A/B, VDDO1 powers CLK1A/B, and so on. Each VDDO pin accepts 1.5 V, 1.8 V, 2.5 V, or 3.3 V, allowing simultaneous LVPECL (3.3 V), LVDS (2.5 V), HCSL (1.8 V), and CMOS (1.5 V) outputs from a single device.

What reference inputs does the SI5338A-B09344-GMR accept, and what are the frequency ranges?

The SI5338A-B09344-GMR accepts five reference input types: differential (5–710 MHz on IN1/IN2 or IN5/IN6), CMOS (5–200 MHz on IN3 or IN4), SSTL/HSTL (5–350 MHz), and crystal (8–30 MHz). All inputs support automatic detection and seamless switching between sources, enabling robust failover and multi-reference system designs.

How is the SI5338A-B09344-GMR programmed, and is configuration retained after power cycle?

The SI5338A-B09344-GMR is programmed via I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which auto-generates register maps and configuration files. Configuration is stored in one-time-programmable (OTP) non-volatile memory, so the SI5338A-B09344-GMR boots with user-defined settings without requiring host initialization.

SI5338A-B09344-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5338A-B09344-GMR FAQ

1.How can I place an order for SI5338A-B09344-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B09344-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B09344-GMR reliable?

The price and inventory of SI5338A-B09344-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B09344-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B09344-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B09344-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B09344-GMR?

SI5338A-B09344-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B09344-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B09344-GMR?

For technical support, including SI5338A-B09344-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B09344-GMR requirements.

6.How does Aetrix verify that SI5338A-B09344-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B09344-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B09344-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B09344-GMR?

All SI5338A-B09344-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B09344-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B09344-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B09344-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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