Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B10382-GMR

Name: SI5338A-B10382-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B10382-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338A-B10382-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338A-B10382-GMR.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,773

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338A-B10382-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch timing, FPGA clocking, and PCIe Gen 4 reference distribution.

For engineers reviewing the SI5338A-B10382-GMR datasheet, SI5338A-B10382-GMR pinout, SI5338A-B10382-GMR application, or SI5338A-B10382-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage per driver (1.5/1.8/2.5/3.3 V), spread-spectrum control (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338A-B10382-GMR implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider followed by a fractional-N MultiSynth™ synthesis stage per output, enabling independent frequency generation with <1 ppb resolution. Its output stage supports mixed signal formats-LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL-each with dedicated VDDO supply and configurable slew rate.

It features loss-of-lock and loss-of-signal alarms, independent phase adjustment (<20 ps steps), glitchless frequency increment/decrement (1 ppm steps), and external feedback mode for zero-delay operation. Input flexibility includes 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential references.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports integer/fractional synthesis with true zero-ppm accuracy
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Formats	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - each independently selectable and voltage-configurable
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V per VDDOx rail
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3
Operating Temperature	–40 °C to +85 °C ambient; qualified per industrial-grade reliability standards

Pinout & Package

SI5338A-B10382-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended input pins	Support 5–200 MHz CMOS inputs; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent differential output drivers; each configurable for LVPECL/LVDS/HCSL/CML
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output pair; enable mixed-voltage clock distribution
VDD	Core supply	1.8/2.5/3.3 V ±10% core power; PSRR optimized for low-noise timing operation
SCL/SDA	I²C interface	Standard SMBus-compatible serial interface (up to 400 kHz); supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status indicator for loss-of-lock and loss-of-signal events
RSVD_GND	Reserved ground	Internal test pin; must be connected to GND per layout guidelines

Key Features

Feature	Design Value
MultiSynth™ synthesis engine	Enables independent, any-frequency generation on all four outputs with <1 ppb resolution and zero ppm error
PCIe Gen 4 Common Clock compliance	0.15–0.45 ps RMS jitter (10 kHz–50 MHz) meets PCIe Base Spec 4.0 rev. 0.5 timing budgets
Independent output voltage per driver	Each VDDOx rail (1.5/1.8/2.5/3.3 V) allows simultaneous LVDS, HCSL, and CMOS outputs without level-shifting
Glitchless frequency tuning	Pin- or I²C-controlled frequency increment/decrement in 1 ppm steps without output interruption
Programmable spread spectrum	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) per output to reduce EMI
External feedback mode	Supports zero-delay clock buffer operation with user-defined feedback path for system-level synchronization

Applications

Ethernet Switch Timing	PCIe Gen 4 Reference Distribution
Use Scenario: Synchronizing multi-port 10 GbE/25 GbE switch ASICs and PHYs with precise inter-port skew control. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz, 312.5 MHz, and 625 MHz clocks with sub-100 ps inter-output skew. Use Value: Eliminates need for multiple discrete oscillators and reduces board area by >60% while meeting IEEE 802.3bj jitter limits.	Use Scenario: Delivering low-jitter reference clocks to CPU, GPU, and NVMe controllers in Gen 4 server platforms. IC Role / Device Role / Timing Role: PCIe Common Clock source generating 100 MHz differential HCSL clocks compliant with SRNS and CEM v4.0. Use Value: Achieves 0.32 ps RMS jitter (Gen 3 SRNS) and 0.45 ps RMS (Gen 4), enabling reliable link training at 16 GT/s.
FPGA and SoC Clocking	Broadcast Video Timing
Use Scenario: Providing multiple synchronized clocks to Xilinx Versal or Intel Agilex FPGAs for transceiver banks, logic fabric, and DDR interfaces. IC Role / Device Role / Timing Role: Configurable quad clock generator delivering 125 MHz LVDS, 200 MHz CMOS, and 300 MHz HCSL simultaneously. Use Value: Enables pin-accurate phase alignment across domains via programmable initial offset (±45 ns) and <20 ps step resolution.	Use Scenario: Generating SMPTE ST 2059-2 PTP-synchronized clocks for 4K/8K video encoders, routers, and IP gateways. IC Role / Device Role / Timing Role: Low-phase-noise clock synthesizer producing 27 MHz, 74.25 MHz, and 148.5 MHz outputs from a 10 MHz GPSDO reference. Use Value: Delivers <1 ps RMS jitter over 12 kHz–20 MHz, satisfying SMPTE RP 188 long-term stability requirements.

Ethernet Switch Timing

PCIe Gen 4 Reference Distribution

Use Scenario: Synchronizing multi-port 10 GbE/25 GbE switch ASICs and PHYs with precise inter-port skew control.

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz, 312.5 MHz, and 625 MHz clocks with sub-100 ps inter-output skew.

Use Value: Eliminates need for multiple discrete oscillators and reduces board area by >60% while meeting IEEE 802.3bj jitter limits.

Use Scenario: Delivering low-jitter reference clocks to CPU, GPU, and NVMe controllers in Gen 4 server platforms.

IC Role / Device Role / Timing Role: PCIe Common Clock source generating 100 MHz differential HCSL clocks compliant with SRNS and CEM v4.0.

Use Value: Achieves 0.32 ps RMS jitter (Gen 3 SRNS) and 0.45 ps RMS (Gen 4), enabling reliable link training at 16 GT/s.

FPGA and SoC Clocking

Broadcast Video Timing

Use Scenario: Providing multiple synchronized clocks to Xilinx Versal or Intel Agilex FPGAs for transceiver banks, logic fabric, and DDR interfaces.

IC Role / Device Role / Timing Role: Configurable quad clock generator delivering 125 MHz LVDS, 200 MHz CMOS, and 300 MHz HCSL simultaneously.

Use Value: Enables pin-accurate phase alignment across domains via programmable initial offset (±45 ns) and <20 ps step resolution.

Use Scenario: Generating SMPTE ST 2059-2 PTP-synchronized clocks for 4K/8K video encoders, routers, and IP gateways.

IC Role / Device Role / Timing Role: Low-phase-noise clock synthesizer producing 27 MHz, 74.25 MHz, and 148.5 MHz outputs from a 10 MHz GPSDO reference.

Use Value: Delivers <1 ps RMS jitter over 12 kHz–20 MHz, satisfying SMPTE RP 188 long-term stability requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08382-GM	Higher integration: 8 outputs, integrated EEPROM, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at high-channel-count SerDes systems (e.g., radar, 5G RU); requires different programming flow and layout	Select when >4 outputs or sub-0.4 ps jitter required; not drop-in compatible due to pin count and EEPROM dependency
ICS853S01IAGLF	Fixed-function 4-output LVDS generator; no I²C programming; 1.2 ps RMS jitter; 100–350 MHz range only	Limited to static clock trees; no spread spectrum, phase adjustment, or multi-format support	Choose for cost-sensitive, low-complexity designs where frequency flexibility and advanced features are unnecessary

Compared with SI5338A-B10382-GMR, Si5332A-D08382-GM offers higher channel density and lower jitter but increases BOM cost and design complexity, while ICS853S01IAGLF provides simpler implementation at the expense of configurability and jitter performance.

Availability

SI5338A-B10382-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 server platforms, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338A-B10382-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with broad portfolio coverage and high-reliability manufacturing.

The Si5338 product line delivers highly flexible, low-jitter clock generation for datacenter, telecom, and broadcast applications where multi-frequency synthesis, PCIe compliance, and compact footprint are critical design requirements.

FAQ

What is the maximum output frequency supported by SI5338A-B10382-GMR?

The SI5338A-B10382-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) per the MultiSynth™ architecture.

Does SI5338A-B10382-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338A-B10382-GMR meets PCIe Gen 4 Common Clock jitter requirements with 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured per specification, verified using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4.

Can SI5338A-B10382-GMR generate different output voltages simultaneously?

Yes, SI5338A-B10382-GMR supports independent VDDOx supplies (1.4–3.63 V) per output pair, enabling concurrent LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs without external level shifters or additional power rails.

How is SI5338A-B10382-GMR programmed in-system?

SI5338A-B10382-GMR uses an I²C/SMBus-compatible serial interface (SCL/SDA) operating up to 400 kHz. Configuration is typically performed via Skyworks' ClockBuilder Pro software, which generates register maps and supports field updates without hardware reset.

What is the thermal resistance (θJA) of SI5338A-B10382-GMR in its QFN package?

The SI5338A-B10382-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions, measured in the standard 4 × 4 mm 24-QFN package with recommended PCB land pattern and thermal pad soldering per JEDEC J-STD-020.

SI5338A-B10382-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5338A-B10382-GMR FAQ

1.How can I place an order for SI5338A-B10382-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B10382-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B10382-GMR reliable?

The price and inventory of SI5338A-B10382-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B10382-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B10382-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B10382-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B10382-GMR?

SI5338A-B10382-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B10382-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B10382-GMR?

For technical support, including SI5338A-B10382-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B10382-GMR requirements.

6.How does Aetrix verify that SI5338A-B10382-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B10382-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B10382-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B10382-GMR?

All SI5338A-B10382-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B10382-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B10382-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B10382-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…