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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338A-B10468-GMR

Name: SI5338A-B10468-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338A-B10468-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338A-B10468-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338A-B10468-GMR.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

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Product details

Overview

SI5338A-B10468-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and Ethernet switch fabric clocks.

For engineers reviewing the SI5338A-B10468-GMR datasheet, SI5338A-B10468-GMR pinout, SI5338A-B10468-GMR application, or SI5338A-B10468-GMR equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis capability (0.16–710 MHz), and I²C-based field reprogramming without hardware change.

Technical Context

The SI5338A-B10468-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. This enables true zero-ppm frequency accuracy on all four outputs simultaneously while supporting integer- and fractional-mode synthesis.

It accepts multiple input references - 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential - and supports external feedback for zero-delay mode. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring via the INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS).
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz).
Input Reference Options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver.
Package & Pins	24-pin QFN (4 × 4 mm); 4 differential clock outputs (CLK0A/B–CLK3A/B), 2 differential inputs (IN1/2, IN5/6), 2 single-ended inputs (IN3/4), I²C interface (SCL/SDA), interrupt (INTR).
Temperature Range	–40 to +85 °C ambient; qualified for industrial and telecom line card deployment.
Power Consumption	45 mA typical core current at 100 MHz on all outputs with 25 MHz reference; <12 mA in buffer-only mode.

Pinout & Package

SI5338A-B10468-GMR is housed in a thermally enhanced 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). The package supports standard reflow profiles and requires controlled impedance routing for differential pairs.

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential Input 1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled by default.
IN3 / IN4	Single-Ended Input	Supports 5–200 MHz CMOS-level reference; VIH = 0.7×VDD, VIL = 0.3×VDD.
IN5 / IN6	Differential Input 2	Second 5–710 MHz differential reference path; enables dual-reference redundancy or frequency translation.
CLK0A / CLK0B – CLK3A / CLK3B	Differential Output Drivers	Four independent LVPECL/LVDS/HCSL/CML outputs; each configurable for format, swing, and common-mode voltage.
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output pair; decoupling required per Skyworks layout guidelines.
SCL / SDA	I²C Interface	Standard SMBus-compatible 100/400 kHz interface; supports write-only configuration and read-back of status registers.
INTR	Interrupt Output	Open-drain active-low signal indicating loss-of-lock, loss-of-signal, or NVM programming completion.
VDD	Core Supply	Single 1.8/2.5/3.3 V supply; PSRR >60 dB across 10 kHz–100 MHz ensures noise immunity.
GND / RSVD_GND	Ground Terminals	Eight dedicated ground pins including thermal pad connection; mandatory for jitter performance and thermal dissipation.

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Generates four independent output frequencies from a single reference with 1 ppb resolution and zero ppm error in integer mode.
Independent Output Voltage Control	Each output pair (CLK0–CLK3) powered by separate VDDOx rail (1.5/1.8/2.5/3.3 V), enabling mixed-voltage system interfacing without level shifters.
Glitchless Frequency Adjustment	Hardware-supported ±1 ppm step increments/decrements via PINC/FDEC pins; no output interruption during dynamic frequency tuning.
Programmable Phase Offset	±45 ns fine phase adjustment per output with <20 ps step resolution; critical for skew alignment in multi-lane SerDes systems.
Spread Spectrum Clocking (SSC)	Configurable on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz frequency range - reduces EMI without affecting timing margin.
PCIe Gen 3 SRNS Compliance	Meets PCIe Base Spec 3.0 SRNS jitter requirements (≤0.32 ps RMS) with PLL bandwidth set to 2–5 MHz and CDR = 10 MHz.

Applications

PCIe Root Complex Timing	Ethernet Switch Fabric Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe endpoints and upstream ports in a server motherboard or NIC. IC Role / Device Role / Timing Role: Quad-output clock generator delivering Common Clock topology with Gen 1–4 compliance and low additive jitter. Use Value: Eliminates four discrete oscillators; enables single-point reconfiguration of all PCIe clocks via I²C during BIOS or firmware update.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet buffers in a Layer-3 switch ASIC. IC Role / Device Role / Timing Role: Any-frequency synthesizer supplying multiple precision clocks from one crystal reference. Use Value: Reduces BOM count and board area; supports dynamic rate adaptation (e.g., 1G ↔ 10G switchover) without hardware change.
Broadcast Video Synchronization	FPGA/Processor Clock Domain Crossing
Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI transceivers, video encoders, and frame synchronizers in broadcast equipment. IC Role / Device Role / Timing Role: Low-jitter, multi-format clock source meeting SMPTE ST 2059-2 PTP traceability requirements. Use Value: Achieves <10 ps cycle-cycle jitter on LVDS outputs; supports programmable phase offset for precise inter-device alignment.	Use Scenario: Providing isolated, voltage-matched clocks to FPGA logic banks (e.g., 100 MHz for AXI, 200 MHz for DDR4 PHY, 300 MHz for PCIe hard IP) and host processor subsystems. IC Role / Device Role / Timing Role: Configurable quad clock generator with independent VDDO per output, enabling direct interface to mixed-voltage SoCs and FPGAs. Use Value: Removes need for external level translators or buffer ICs; simplifies power domain partitioning and timing closure.

PCIe Root Complex Timing

Ethernet Switch Fabric Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe endpoints and upstream ports in a server motherboard or NIC.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering Common Clock topology with Gen 1–4 compliance and low additive jitter.

Use Value: Eliminates four discrete oscillators; enables single-point reconfiguration of all PCIe clocks via I²C during BIOS or firmware update.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet buffers in a Layer-3 switch ASIC.

IC Role / Device Role / Timing Role: Any-frequency synthesizer supplying multiple precision clocks from one crystal reference.

Use Value: Reduces BOM count and board area; supports dynamic rate adaptation (e.g., 1G ↔ 10G switchover) without hardware change.

Broadcast Video Synchronization

FPGA/Processor Clock Domain Crossing

Use Scenario: Delivering genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI transceivers, video encoders, and frame synchronizers in broadcast equipment.

IC Role / Device Role / Timing Role: Low-jitter, multi-format clock source meeting SMPTE ST 2059-2 PTP traceability requirements.

Use Value: Achieves <10 ps cycle-cycle jitter on LVDS outputs; supports programmable phase offset for precise inter-device alignment.

Use Scenario: Providing isolated, voltage-matched clocks to FPGA logic banks (e.g., 100 MHz for AXI, 200 MHz for DDR4 PHY, 300 MHz for PCIe hard IP) and host processor subsystems.

IC Role / Device Role / Timing Role: Configurable quad clock generator with independent VDDO per output, enabling direct interface to mixed-voltage SoCs and FPGAs.

Use Value: Removes need for external level translators or buffer ICs; simplifies power domain partitioning and timing closure.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B09469-GM	Same Si5338A die, factory-programmed for fixed 100/125/156.25/312.5 MHz outputs; no I²C EEPROM; pre-configured for Ethernet switch use case.	Limited to predefined frequencies; no field reprogramming; optimized for plug-and-play 10GbE timing.	Select when fixed-frequency operation and reduced configuration overhead outweigh need for runtime flexibility.
LMK04832ISQE/NOPB	Two PLLs (jitter cleaner + synthesizer), higher integration (integrated LDOs, SPI interface), 0.18 ps RMS jitter; larger 48-QFN package.	Better suited for ultra-low-jitter applications (e.g., RF sampling clocks, radar), but higher cost and power (120 mA typical).	Select when sub-0.2 ps RMS jitter and dual-loop cleaning are required, and board space allows 48-pin footprint.

Compared with Si5338A-B09469-GM, SI5338A-B10468-GMR offers full I²C programmability and field-updatable configurations; compared with LMK04832ISQE/NOPB, it delivers lower cost, smaller footprint, and adequate jitter for PCIe Gen 4 and 10GbE, but lacks integrated jitter cleaning and SPI support.

Availability

SI5338A-B10468-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 root complex timing, 10GbE switch fabric synchronization, and broadcast video genlock applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338A-B10468-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family was designed specifically for high-density, multi-protocol timing consolidation in networking, computing, and communications equipment - enabling replacement of multiple oscillators with a single programmable device.

FAQ

What is the primary function of the SI5338A-B10468-GMR in a PCIe Gen 4 system?

The SI5338A-B10468-GMR serves as a quad-output common clock generator delivering compliant 100 MHz reference signals to root ports and endpoints. It meets PCIe Gen 4 jitter requirements (≤0.45 ps RMS) using its MultiSynth™ engine and configurable PLL bandwidth, and supports I²C-based runtime frequency updates without disrupting link training - a key advantage over fixed-frequency alternatives. SI5338A-B10468-GMR enables single-source timing control across heterogeneous PCIe lanes.

Does the SI5338A-B10468-GMR support spread spectrum clocking (SSC), and how is it configured?

Yes, SI5338A-B10468-GMR supports fully programmable SSC on any output: spread range (0.5–5.0%), modulation rate (33–63 kHz), and center frequency (5–350 MHz) are all configurable via I²C registers. SSC is applied digitally within the MultiSynth™ stage, preserving output edge integrity and avoiding analog modulation artifacts. Configuration is performed using ClockBuilder Pro software or direct register writes; default setting is 0.5% down-spread at ~31.5 kHz.

Can the SI5338A-B10468-GMR generate different output formats simultaneously (e.g., LVDS and HCSL)?

Yes, SI5338A-B10468-GMR supports mixed output formats across its four channels: CLK0A/B may be configured as LVDS, CLK1A/B as HCSL, CLK2A/B as LVPECL, and CLK3A/B as CMOS - all concurrently. Each output driver is independently selectable for format, voltage level (1.5/1.8/2.5/3.3 V), and termination. This eliminates need for external level translators in multi-standard systems like converged network adapters.

What is the minimum input reference frequency supported by the SI5338A-B10468-GMR in PLL mode?

In PLL mode, SI5338A-B10468-GMR requires a minimum input reference frequency of 5 MHz for all input types (differential, CMOS, SSTL/HSTL). Crystal inputs are limited to 8–30 MHz per datasheet specifications. Below 5 MHz, the device enters clock buffer (PLL bypass) mode only - where loss-of-signal detection and full synthesis features are disabled. SI5338A-B10468-GMR does not support sub-5 MHz PLL operation.

How is phase alignment between outputs achieved on the SI5338A-B10468-GMR?

SI5338A-B10468-GMR provides per-output programmable initial phase offset from –45 ns to +45 ns in <20 ps steps, plus real-time phase increment/decrement via hardware pins (PINC/FDEC) or I²C. Alignment is maintained across temperature and voltage via on-chip calibration. For integer-related frequencies, output-to-output skew is guaranteed ≤100 ps, enabling tight timing margins in multi-lane interfaces like PCIe x16 or 100G CAUI-4. SI5338A-B10468-GMR achieves this without external delay lines or manual PCB tuning.

SI5338A-B10468-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5338A-B10468-GMR FAQ

1.How can I place an order for SI5338A-B10468-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338A-B10468-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338A-B10468-GMR reliable?

The price and inventory of SI5338A-B10468-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338A-B10468-GMR is usually 5 days.

3.What payment methods are accepted for SI5338A-B10468-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338A-B10468-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338A-B10468-GMR?

SI5338A-B10468-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338A-B10468-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338A-B10468-GMR?

For technical support, including SI5338A-B10468-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338A-B10468-GMR requirements.

6.How does Aetrix verify that SI5338A-B10468-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338A-B10468-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338A-B10468-GMR meets industry standards.

7.What is the process for return or replacement of SI5338A-B10468-GMR?

All SI5338A-B10468-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338A-B10468-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338A-B10468-GMR part is unused and in its original packaging.

Return procedure for SI5338A-B10468-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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