Skyworks Solutions Inc. SI5338A-B15673-GMR

Overview

SI5338A-B15673-GMR from Skyworks Solutions is an I²C-programmable, quad-output clock generator using MultiSynth™ technology to synthesize any frequency on each of four independent differential outputs with 0 ppm precision. It delivers 0.7 ps RMS typical phase jitter, supports PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operates from a single 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It serves as a drop-in replacement for up to four crystal oscillators in high-speed serial interface timing.

For engineers reviewing the SI5338A-B15673-GMR datasheet, SI5338A-B15673-GMR pinout, SI5338A-B15673-GMR application, or SI5338A-B15673-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), programmable phase adjustment (<20 ps steps), spread-spectrum capability (0.5–5.0% spread, 33–63 kHz modulation), and support for differential inputs up to 710 MHz.

Technical Context

The SI5338A-B15673-GMR implements a two-stage synthesis architecture: a primary PLL with 1.6 MHz loop bandwidth locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers - each with dedicated M/N/R dividers - enabling integer or fractional output generation from 0.16 MHz to 710 MHz. Each output stage supports format-selectable drivers (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) with independent VDDO supplies.

It features loss-of-lock and loss-of-signal alarms, glitchless frequency increment/decrement in 1 ppm steps via pin or I²C control, and programmable initial phase offset (±45 ns). The device includes on-chip OTP NVM for factory or field programming, and supports external feedback for zero-delay mode operation - critical for low-latency timing distribution in FPGA and processor clock trees.

Key Specifications

Pinout & Package

SI5338A-B15673-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed across the Si5338 family and match the documented top-view layout.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with SI5338A-B15673-GMR, Si5338A-B15674-GMR offers identical performance and pinout but different factory defaults, while LMK04832ISQE/NOPB provides superior jitter cleaning at the cost of size, power, and complexity - making it appropriate only for specialized RF or JESD204B systems.

Availability

SI5338A-B15673-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching infrastructure, broadcast video equipment, and FPGA-based test instrumentation requiring stable component supply and long-term lifecycle support.

Supply support for SI5338A-B15673-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed to replace multiple discrete oscillators with a single, software-programmable clock generator for high-speed serial interfaces - targeting PCIe, Ethernet, Fibre Channel, and broadcast video timing applications where flexibility, low jitter, and space savings are critical.

FAQ

What is the factory-programmed configuration of SI5338A-B15673-GMR?

The SI5338A-B15673-GMR is pre-programmed with a specific output configuration optimized for PCIe Gen 4 timing: four HCSL outputs at 100 MHz, with spread-spectrum disabled and phase alignment enabled. This configuration is stored in on-chip OTP memory and can be reprogrammed via I²C using ClockBuilder Pro software without requiring external programming hardware. The part number suffix "B15673" directly encodes this factory setting.

Does SI5338A-B15673-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338A-B15673-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical) when configured with a PLL bandwidth of 2–5 MHz and CDR set to 10 MHz. This mode requires disabling spread spectrum and selecting integer-mode synthesis on the relevant output; validation is confirmed per PCI Express Base Specification 4.0 rev. 0.5 and measured using the Skyworks PCIe Clock Jitter Tool.

Can SI5338A-B15673-GMR generate four different frequencies above 350 MHz simultaneously?

No. SI5338A-B15673-GMR can output only two unique frequencies above 350 MHz simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints and internal divider architecture. All four outputs may operate above 350 MHz only if they share one of those two frequencies; other outputs must be ≤350 MHz or use integer-related harmonics within the same VCO division scheme.

What is the maximum differential input frequency supported by SI5338A-B15673-GMR?

The maximum differential input frequency supported by SI5338A-B15673-GMR is 710 MHz, applicable to AC-coupled differential clock inputs on pins IN1/IN2 and IN5/IN6. This specification assumes proper termination with a 100 Ω external resistor and input slew rate >0.3 V/ns for optimal jitter performance, as verified in Skyworks' characterization lab per Table 6 of the datasheet.

Is SI5338A-B15673-GMR pin-compatible with other Si5338 variants like SI5338A-B-GM?

Yes, SI5338A-B15673-GMR is fully pin-compatible with all Si5338A variants in the 24-QFN package, including SI5338A-B-GM. The pinout, package dimensions, thermal pad layout, and power sequencing requirements are identical across the family. Differences exist only in factory-programmed OTP content and ordering-specific marking - not in electrical or mechanical interface behavior.