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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338B-B04160-GMR

Name: SI5338B-B04160-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338B-B04160-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338B-B04160-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338B-B04160-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338B-B04160-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in Ethernet switch/router and FPGA clocking systems.

For engineers reviewing the SI5338B-B04160-GMR datasheet, SI5338B-B04160-GMR pinout, SI5338B-B04160-GMR application, or SI5338B-B04160-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis, independent per-output voltage (1.5/1.8/2.5/3.3 V), ±20 ps phase step resolution, and 4×4 mm 24-QFN package with I²C/SMBus configuration interface.

Technical Context

The SI5338B-B04160-GMR implements a two-stage PLL architecture: a high-performance integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output with true zero-ppm accuracy. Each output driver supports format and voltage selection, spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate), and glitchless frequency increment/decrement in 1 ppm steps.

It features loss-of-lock and loss-of-signal alarms, programmable initial phase offset (±45 ns), and external feedback mode enabling zero-delay operation. Core supply operates at 1.8/2.5/3.3 V with 45 mA typical current draw, and the device is qualified for –40 to +85 °C industrial temperature range.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements; enables clean timing for high-speed SerDes interfaces
Output Frequency Range	0.16–710 MHz - covers PCIe (100 MHz), Ethernet (125/156.25 MHz), Fibre Channel (1.0625 GHz via Fvco/4), and broadcast video (27/74.25 MHz)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system-level clock sourcing
Output Format Flexibility	LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL - allows direct interfacing with FPGAs, processors, switches, and PHYs without level-shifting components
Per-Output Supply Voltage	1.5/1.8/2.5/3.3 V - supports mixed-voltage SoC/FPGA designs and eliminates need for external LDOs per clock domain
Package	24-pin QFN, 4 × 4 mm - space-efficient footprint compatible with high-density PCB layouts and automated assembly
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments without derating

Pinout & Package

SI5338B-B04160-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref 2), IN5/IN6 (differential ref 3), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	LVPECL/LVDS/HCSL-configurable clock output; supports 0.16–710 MHz with independent voltage (VDDO0) and format control
CLK1A / CLK1B	Differential Output Pair 1	Independent synthesis path; enables asynchronous frequency generation (e.g., 100 MHz PCIe + 125 MHz GbE on same device)
CLK2A / CLK2B	Differential Output Pair 2	Supports spread-spectrum modulation (0.5–5.0% down-spread) for EMI reduction in dense board layouts
CLK3A / CLK3B	Differential Output Pair 3	Programmable phase offset (±45 ns, <20 ps step) for skew alignment in multi-lane SerDes or memory interfaces
IN1 / IN2	Differential Input 1	Primary reference input; accepts 5–710 MHz LVDS/CML signals with internal 100 Ω termination and 0.3 V/ns slew requirement
SCL / SDA	I²C Serial Interface	Standard-compliant SMBus interface (up to 400 kHz) for runtime reconfiguration without reset or power cycle
INTR	Interrupt Output	Open-drain status signal asserting on loss-of-lock, loss-of-signal, or register-access error; simplifies system monitoring
VDDO0–VDDO3	Output Buffer Supplies	Four independent 1.4–3.63 V supplies enabling mixed-voltage clock domains (e.g., 1.8 V FPGA core + 3.3 V legacy PHY)

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Generates four independent, zero-ppm-accurate output frequencies from a single reference-eliminates multiple XO BOM line items and layout complexity
PCIe Gen 1/2/3/4 Common Clock & Gen 3 SRNS Compliance	Validated 0.11–0.45 ps RMS jitter performance ensures interoperability with Intel/AMD/NVIDIA root complexes and endpoints without additional jitter cleaning
Independent Per-Output Voltage and Format	Each output driver selects voltage (1.5/1.8/2.5/3.3 V) and format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) in real time-enables direct connection to heterogeneous logic families
Glitchless Frequency Adjustment	1 ppm step size with hardware pin control (PINC/FDEC) allows dynamic clock scaling during operation-critical for power-aware FPGA partial reconfiguration
Programmable Spread Spectrum	Configurable spread (0.5–5.0%), rate (33–63 kHz), and direction per output-reduces peak EMI by >10 dB without affecting timing margins
External Feedback Mode	Enables zero-delay buffer operation using CLKOUT as feedback-preserves input clock phase integrity for synchronous backplane applications

Applications

Ethernet Switch/Router Timing	PCIe Gen 3/4 Clocking
Use Scenario: High-port-count 1/10 GbE switches requiring precise 125 MHz and 156.25 MHz clocks for MAC/PHY synchronization and packet buffering. IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter outputs: two 125 MHz LVDS clocks for SFP+ lanes, one 156.25 MHz HCSL for CPU interconnect, and one 25 MHz CMOS for management MCU. Use Value: Replaces four discrete oscillators; reduces board area by 65% and eliminates inter-clock skew between data paths.	Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, CXL memory expansion, and integrated GPU-all requiring synchronized 100 MHz reference clocks. IC Role / Device Role / Timing Role: PCIe Common Clock source delivering four 100 MHz HCSL outputs compliant with PCIe Base Spec 4.0 SRNS requirements (≤0.32 ps RMS jitter). Use Value: Meets Gen 4 jitter spec without external jitter cleaners; supports hot-plug and link training via I²C reprogramming.
Broadcast Video/Audio Sync	FPGA & Processor Clocking
Use Scenario: SMPTE ST 2110 IP media gateway needing genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks for SDI-to-IP conversion and audio sample rate conversion. IC Role / Device Role / Timing Role: Multi-format clock synthesizer generating three exact-frequency outputs with sub-20 ps phase step resolution for frame-accurate lip-sync alignment. Use Value: Eliminates need for separate video-specific clock ICs; enables software-defined timing via ClockBuilder Pro configuration.	Use Scenario: Xilinx Versal ACAP-based edge AI inference platform requiring 500 MHz PL clock, 300 MHz PS clock, 100 MHz DDR4 interface clock, and 25 MHz debug UART clock. IC Role / Device Role / Timing Role: Centralized clock source with independent voltage per output: 1.0 V for PL, 1.8 V for PS, 1.2 V for DDR4, and 3.3 V for UART-no external level shifters required. Use Value: Reduces power delivery complexity; enables dynamic frequency scaling of PL clock via PINC/FDEC pins during workload changes.

Ethernet Switch/Router Timing

PCIe Gen 3/4 Clocking

Use Scenario: High-port-count 1/10 GbE switches requiring precise 125 MHz and 156.25 MHz clocks for MAC/PHY synchronization and packet buffering.

IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter outputs: two 125 MHz LVDS clocks for SFP+ lanes, one 156.25 MHz HCSL for CPU interconnect, and one 25 MHz CMOS for management MCU.

Use Value: Replaces four discrete oscillators; reduces board area by 65% and eliminates inter-clock skew between data paths.

Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, CXL memory expansion, and integrated GPU-all requiring synchronized 100 MHz reference clocks.

IC Role / Device Role / Timing Role: PCIe Common Clock source delivering four 100 MHz HCSL outputs compliant with PCIe Base Spec 4.0 SRNS requirements (≤0.32 ps RMS jitter).

Use Value: Meets Gen 4 jitter spec without external jitter cleaners; supports hot-plug and link training via I²C reprogramming.

Broadcast Video/Audio Sync

FPGA & Processor Clocking

Use Scenario: SMPTE ST 2110 IP media gateway needing genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks for SDI-to-IP conversion and audio sample rate conversion.

IC Role / Device Role / Timing Role: Multi-format clock synthesizer generating three exact-frequency outputs with sub-20 ps phase step resolution for frame-accurate lip-sync alignment.

Use Value: Eliminates need for separate video-specific clock ICs; enables software-defined timing via ClockBuilder Pro configuration.

Use Scenario: Xilinx Versal ACAP-based edge AI inference platform requiring 500 MHz PL clock, 300 MHz PS clock, 100 MHz DDR4 interface clock, and 25 MHz debug UART clock.

IC Role / Device Role / Timing Role: Centralized clock source with independent voltage per output: 1.0 V for PL, 1.8 V for PS, 1.2 V for DDR4, and 3.3 V for UART-no external level shifters required.

Use Value: Reduces power delivery complexity; enables dynamic frequency scaling of PL clock via PINC/FDEC pins during workload changes.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06189-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), but fixed 4-output LVDS-only; no HCSL/CMOS support	Best suited for PCIe Gen 5 and ultra-low-jitter applications where crystal integration and smaller jitter budget are critical	Select when crystal integration and sub-0.4 ps jitter are mandatory; avoid if HCSL/CMOS outputs or external crystal flexibility are needed
ICS8430I-01T	Non-programmable, fixed-frequency quad LVDS generator; 1.2 ps RMS jitter; no I²C interface or spread spectrum	Targeted at cost-sensitive, high-volume applications with static clock trees (e.g., legacy storage controllers)	Select only for fixed-frequency, non-reconfigurable designs where programmability and jitter headroom are not required

Compared with Si5332A-D06189-GM and ICS8430I-01T, the SI5338B-B04160-GMR uniquely balances field-programmability, multi-format flexibility, and PCIe Gen 4 compliance in a single 4×4 mm package-making it optimal for prototyping, multi-platform reuse, and evolving interface standards.

Availability

SI5338B-B04160-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 4 clocking, broadcast video sync, and FPGA processor clocking requiring stable component supply across design-in, NPI, and production ramp phases.

Supply support for SI5338B-B04160-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in precision timing, RF, and connectivity solutions for infrastructure, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed digital systems-including datacenter switches, 5G baseband units, and broadcast equipment-where frequency agility and timing integrity are mission-critical.

FAQ

What is the primary function of the SI5338B-B04160-GMR?

The SI5338B-B04160-GMR is an I²C-programmable quad clock generator that synthesizes four independent, zero-ppm-accurate output frequencies from a single reference input. It serves as a drop-in replacement for up to four discrete crystal oscillators in applications like PCIe, Ethernet, and FPGA clocking-delivering 0.7 ps RMS typical phase jitter and supporting LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL output formats.

Does the SI5338B-B04160-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338B-B04160-GMR meets PCIe Gen 4 Common Clock specifications with ≤0.45 ps RMS jitter (10 kHz–50 MHz) when configured per Skyworks' validated settings. Its MultiSynth™ architecture and optimized PLL loop bandwidth (2–5 MHz) ensure compliance with PCI-SIG Base Specification 4.0, including SRNS mode for Gen 3 and common clock mode for Gen 4.

Can the SI5338B-B04160-GMR generate different output voltages simultaneously?

Yes, the SI5338B-B04160-GMR supports independent output supply voltages per channel via VDDO0–VDDO3 pins, allowing simultaneous 1.8 V, 2.5 V, 3.3 V, and 1.5 V outputs. This enables direct interfacing with mixed-voltage SoCs and FPGAs-e.g., 1.8 V for FPGA fabric, 3.3 V for legacy peripherals, and 1.5 V for DDR4 PHY-without external level shifters.

How is the SI5338B-B04160-GMR programmed and configured?

The SI5338B-B04160-GMR is programmed via its I²C/SMBus-compatible serial interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration includes output frequencies, formats, voltages, spread-spectrum parameters, and phase offsets. Pre-programmed devices ship with factory-default settings; field updates require no hardware reset and support runtime reconfiguration.

What package type and pin count does the SI5338B-B04160-GMR use?

The SI5338B-B04160-GMR uses a 24-pin QFN package measuring 4 × 4 mm with an exposed thermal pad. It features four differential output pairs (CLK0A/B through CLK3A/B), six reference inputs (IN1–IN6), four independent output supply pins (VDDO0–VDDO3), core supply (VDD), I²C interface (SCL/SDA), interrupt output (INTR), and reserved ground (RSVD_GND).

SI5338B-B04160-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338B-B04160-GMR FAQ

1.How can I place an order for SI5338B-B04160-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338B-B04160-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338B-B04160-GMR reliable?

The price and inventory of SI5338B-B04160-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B04160-GMR is usually 5 days.

3.What payment methods are accepted for SI5338B-B04160-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B04160-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338B-B04160-GMR?

SI5338B-B04160-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338B-B04160-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338B-B04160-GMR?

For technical support, including SI5338B-B04160-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B04160-GMR requirements.

6.How does Aetrix verify that SI5338B-B04160-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338B-B04160-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B04160-GMR meets industry standards.

7.What is the process for return or replacement of SI5338B-B04160-GMR?

All SI5338B-B04160-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B04160-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338B-B04160-GMR part is unused and in its original packaging.

Return procedure for SI5338B-B04160-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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