Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338B-B04183-GM

Name: SI5338B-B04183-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338B-B04183-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338B-B04183-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338B-B04183-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,489

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338B-B04183-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and MultiSynth™ frequency synthesis supporting 0.16–710 MHz output ranges. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338B-B04183-GM datasheet, SI5338B-B04183-GM pinout, SI5338B-B04183-GM application, or SI5338B-B04183-GM equivalent, key selection criteria include PCIe Gen 4 common-clock jitter (≤0.45 ps RMS), independent per-output voltage (1.5/1.8/2.5/3.3 V), spread-spectrum control (0.5–5.0% down-spread), and 24-QFN package compatibility with board-level thermal management.

Technical Context

The SI5338B-B04183-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its input supports eight clock sources-differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or 8–30 MHz crystal-with loss-of-signal detection on all inputs.

Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent supply voltage (VDDOx = 1.5/1.8/2.5/3.3 V), programmable phase offset (±45 ns, <20 ps step), and glitchless frequency increment/decrement (1 ppm steps). External feedback enables zero-delay mode for synchronous systems.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 4 common-clock jitter requirement (≤0.45 ps RMS) under specified test conditions
Output Frequency Range	0.16–710 MHz - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, Fibre Channel 1.0625 GHz (via Fvco/4), and broadcast video 27/74.25 MHz
Input Reference Support	8–30 MHz crystal or 5–710 MHz differential - enables direct replacement of legacy XO-based clock trees without redesign
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.5/1.8/2.5/3.3 V - allows mixed-voltage system integration with FPGA I/O banks and ASIC clock domains
Package	24-pin QFN, 4 × 4 mm - footprint-compatible with industry-standard clock IC layouts and supports ≤37 °C/W thermal resistance
PCIe Compliance	Gen 1/2/3/4 Common Clock & Gen 3 SRNS - validated per Intel Clock Jitter Tool v1.6.4 using HCSL 100 MHz outputs
Spread Spectrum	0.5–5.0% down-spread, 33–63 kHz modulation - reduces EMI in dense PCB environments without violating PCIe spectral mask

Pinout & Package

SI5338B-B04183-GM uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed across Si5338 variants and match the functional block diagram layout.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential clock inputs	Accept 5–710 MHz AC-coupled LVDS/CML; internal 100 Ω termination enables direct connection to SERDES reference clocks
IN3/IN4	Single-ended clock inputs	Support 5–200 MHz CMOS; slew-rate >1 V/ns required for optimal jitter performance
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent drivers; each configurable as LVPECL/LVDS/HCSL/CML with per-output VDDO supply
VDDO0–VDDO3	Output buffer supplies	Enable mixed-signal timing: e.g., CLK0 = 1.8 V LVDS for FPGA, CLK1 = 3.3 V CMOS for microcontroller
SCL/SDA	I²C interface	Standard SMBus-compatible 100/400 kHz operation; supports in-system programming without reset
INTR	Interrupt output	Open-drain status flag for loss-of-lock or loss-of-signal events; simplifies real-time fault monitoring

Key Features

Feature	Design Value
Independent per-output voltage control	Enables direct interfacing to heterogeneous logic families (e.g., 1.8 V FPGA bank + 3.3 V MCU) without level shifters
Programmable phase offset (±45 ns, <20 ps step)	Allows precise skew alignment between PCIe root complex and endpoint clocks to meet setup/hold timing margins
Glitchless frequency increment/decrement (1 ppm steps)	Supports dynamic frequency scaling in adaptive computing platforms without clock interruption or metastability risk
External feedback mode	Configures zero-delay buffer operation for synchronous backplane timing where reference and output must be phase-aligned
Loss-of-signal and loss-of-lock alarms	Provides deterministic fault signaling via INTR pin for system-level health monitoring and fail-safe recovery

Applications

PCIe Gen 4 Switch Timing	Ethernet 10GbE PHY Clocking
Use Scenario: Providing synchronized 100 MHz common reference clocks to multiple PCIe Gen 4 switches in a server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter (<0.45 ps RMS) HCSL clocks with matched propagation delay and skew-controlled phase alignment. Use Value: Eliminates need for four discrete oscillators while meeting PCIe Gen 4 common-clock jitter spec and reducing BOM count by 75%.	Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10GbE KR/KR4 PHYs and MAC layers in telecom line cards. IC Role / Device Role / Timing Role: Dual-frequency synthesis engine with independent LVDS outputs at different voltages (2.5 V for PHY, 1.8 V for MAC). Use Value: Achieves sub-1 ps RMS jitter at both frequencies simultaneously, enabling clean eye diagrams and BER <10⁻¹² without external jitter cleaners.
Broadcast Video Sync Generator	FPGA-Based Video Processing
Use Scenario: Deriving SMPTE ST 2082 (27 MHz), ST 292 (27 MHz), and ST 424 (74.25 MHz) reference clocks from a single 27 MHz crystal in broadcast camera head electronics. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating three exact-frequency outputs with zero ppm error and <10 ps cycle-cycle jitter. Use Value: Replaces crystal oscillator + divider chain, eliminating frequency drift and reducing PCB area by 60%.	Use Scenario: Supplying 100 MHz LVDS, 200 MHz CMOS, and 300 MHz LVDS clocks to Xilinx Versal ACAP fabric, memory controller, and transceivers. IC Role / Device Role / Timing Role: Configurable multi-format clock source with per-output voltage (1.8 V LVDS, 3.3 V CMOS, 2.5 V LVDS) and independent phase tuning. Use Value: Enables full utilization of FPGA I/O banks without external level translation or discrete clock buffers.

PCIe Gen 4 Switch Timing

Ethernet 10GbE PHY Clocking

Use Scenario: Providing synchronized 100 MHz common reference clocks to multiple PCIe Gen 4 switches in a server backplane.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter (<0.45 ps RMS) HCSL clocks with matched propagation delay and skew-controlled phase alignment.

Use Value: Eliminates need for four discrete oscillators while meeting PCIe Gen 4 common-clock jitter spec and reducing BOM count by 75%.

Use Scenario: Generating 156.25 MHz and 312.5 MHz clocks for 10GbE KR/KR4 PHYs and MAC layers in telecom line cards.

IC Role / Device Role / Timing Role: Dual-frequency synthesis engine with independent LVDS outputs at different voltages (2.5 V for PHY, 1.8 V for MAC).

Use Value: Achieves sub-1 ps RMS jitter at both frequencies simultaneously, enabling clean eye diagrams and BER <10⁻¹² without external jitter cleaners.

Broadcast Video Sync Generator

FPGA-Based Video Processing

Use Scenario: Deriving SMPTE ST 2082 (27 MHz), ST 292 (27 MHz), and ST 424 (74.25 MHz) reference clocks from a single 27 MHz crystal in broadcast camera head electronics.

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating three exact-frequency outputs with zero ppm error and <10 ps cycle-cycle jitter.

Use Value: Replaces crystal oscillator + divider chain, eliminating frequency drift and reducing PCB area by 60%.

Use Scenario: Supplying 100 MHz LVDS, 200 MHz CMOS, and 300 MHz LVDS clocks to Xilinx Versal ACAP fabric, memory controller, and transceivers.

IC Role / Device Role / Timing Role: Configurable multi-format clock source with per-output voltage (1.8 V LVDS, 3.3 V CMOS, 2.5 V LVDS) and independent phase tuning.

Use Value: Enables full utilization of FPGA I/O banks without external level translation or discrete clock buffers.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B04183-GM	Same pinout and register map; differs only in factory-programmed NVM configuration (A vs B variant)	Identical electrical specs and use cases; B variant includes pre-loaded PCIe Gen 4 profile	Select SI5338B-B04183-GM when PCIe Gen 4 SRNS compliance is required out-of-box
LMK04832ISQE/NOPB	Two PLLs + 14 outputs; higher power (125 mA); larger 64-QFN package; no integrated crystal drive	Targeted at ultra-low-jitter (<0.1 ps) RF and instrumentation; over-specified for PCIe/10GbE cost-sensitive designs	Choose LMK04832 only if >12 outputs or sub-0.2 ps RMS jitter is mandatory

Compared with Si5338A-B04183-GM, the SI5338B-B04183-GM delivers identical hardware functionality but ships with PCIe Gen 4-optimized firmware; versus LMK04832, it offers 50% lower BOM cost and 60% smaller footprint at the expense of output count and extreme-jitter performance.

Availability

SI5338B-B04183-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE PHY clocking, and broadcast video sync generation requiring stable component supply across industrial temperature range (–40 to +85 °C).

Supply support for SI5338B-B04183-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in space-constrained systems requiring multi-protocol timing (PCIe, Ethernet, Fibre Channel, broadcast video) with minimal external components.

FAQ

What is the guaranteed phase jitter performance of the SI5338B-B04183-GM under PCIe Gen 4 common-clock conditions?

The SI5338B-B04183-GM delivers ≤0.45 ps RMS phase jitter (1.5–50 MHz band) when configured per PCIe Gen 4 common-clock requirements using HCSL 100 MHz outputs and a 25 MHz reference. This value is measured with the Skyworks PCIe Clock Jitter Tool v1.6.4 and complies with PCI-SIG Base Specification 4.0 rev. 0.5. The SI5338B-B04183-GM achieves this using its patented MultiSynth™ architecture and optimized PLL loop bandwidth of 2–4 MHz.

Does the SI5338B-B04183-GM support direct connection to a 27 MHz crystal, and what load capacitance is required?

Yes, the SI5338B-B04183-GM supports 8–30 MHz crystals including 27 MHz. It provides on-chip differential load capacitance of 11–13 pF (supported) with 17–19 pF recommended. For a standard 18 pF crystal, no external capacitors are needed. The SI5338B-B04183-GM's crystal driver circuitry is optimized for ESR ≤75 Ω at 27 MHz, ensuring reliable start-up and low-phase-noise operation.

Can the SI5338B-B04183-GM generate two different frequencies above 350 MHz simultaneously, and what are the constraints?

Yes, the SI5338B-B04183-GM can generate two unique frequencies above 350 MHz simultaneously-specifically Fvco/4 and Fvco/6-provided both fall within the 550–710 MHz range. This capability is enabled by the MultiSynth™ architecture's dual-path synthesis stage. However, no more than two such high-frequency outputs may be active concurrently. All other outputs must remain ≤350 MHz. The SI5338B-B04183-GM's datasheet specifies this limitation explicitly in Table 6, Note 6.

How does the SI5338B-B04183-GM handle loss-of-signal detection on its differential inputs, and what is the response time?

The SI5338B-B04183-GM monitors all differential inputs (IN1/IN2, IN5/IN6) for loss-of-signal (LOS) with a typical detection time of 2.6–5 µs and release time of 0.01–1 µs. Detection is triggered when differential swing falls below 0.4 V_PP. The event asserts the open-drain INTR pin and sets corresponding status bits in the device's interrupt register. This behavior is fully documented in Table 5 and Section 3.6 of the SI5338B-B04183-GM datasheet.

Is the SI5338B-B04183-GM compatible with ClockBuilder Pro software, and what configuration files are included?

Yes, the SI5338B-B04183-GM is fully supported by Skyworks' ClockBuilder Pro software (v3.0+). The software includes pre-validated configuration profiles for PCIe Gen 4 common clock, 10GbE KR, and SMPTE ST 2082/292/424 video standards. Users can generate custom .cbs files for the SI5338B-B04183-GM, program OTP memory via I²C, and export register maps for integration into boot firmware. ClockBuilder Pro is available free at skyworksinc.com/en/Application-Pages/Clockbuilder-Pro-Software.

SI5338B-B04183-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338B-B04183-GM FAQ

1.How can I place an order for SI5338B-B04183-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338B-B04183-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338B-B04183-GM reliable?

The price and inventory of SI5338B-B04183-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B04183-GM is usually 5 days.

3.What payment methods are accepted for SI5338B-B04183-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B04183-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338B-B04183-GM?

SI5338B-B04183-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338B-B04183-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338B-B04183-GM?

For technical support, including SI5338B-B04183-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B04183-GM requirements.

6.How does Aetrix verify that SI5338B-B04183-GM is sourced from the original manufacturer or authorized distributors?

All SI5338B-B04183-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B04183-GM meets industry standards.

7.What is the process for return or replacement of SI5338B-B04183-GM?

All SI5338B-B04183-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B04183-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338B-B04183-GM part is unused and in its original packaging.

Return procedure for SI5338B-B04183-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…