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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338B-B04183-GMR

Name: SI5338B-B04183-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338B-B04183-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338B-B04183-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338B-B04183-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338B-B04183-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ) across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, supporting PCIe Gen 1–4 and Ethernet timing in telecom line cards and FPGA-based systems.

For engineers reviewing the SI5338B-B04183-GMR datasheet, SI5338B-B04183-GMR pinout, SI5338B-B04183-GMR application, or SI5338B-B04183-GMR equivalent, key selection criteria include differential output jitter compliance with PCIe Gen 4 SRNS (0.15–0.45 ps RMS), independent per-output voltage control (1.5–3.3 V), and 4×4 mm 24-QFN package integration for space-constrained high-speed designs.

Technical Context

The SI5338B-B04183-GMR implements a two-stage PLL architecture: a reference-stage PLL locks to an external crystal (8–30 MHz) or CMOS/differential input (5–710 MHz), followed by four independent MultiSynth™ fractional-N synthesizers enabling any-frequency generation on each of four output drivers. Each synthesizer supports integer or fractional mode with <1 ppb resolution.

Output stage configuration includes programmable drive strength, slew rate, and format-specific termination; all outputs support independent phase adjustment (<20 ps steps), frequency increment/decrement (1 ppm steps), and spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate). The device operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 Common Clock and SRNS requirements.
Output Frequency Range	0.16–710 MHz depending on format: LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz.
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3.
Operating Temperature	–40 °C to +85 °C ambient; validated for industrial and telecom infrastructure environments.
Interface	I²C/SMBus-compatible serial interface (up to 400 kHz); supports ClockBuilder Pro programming.

Pinout & Package

SI5338B-B04183-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow standard Si5338 top-view layout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref 2/3), IN5/IN6 (differential ref 4/5), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C bus), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	LVPECL/LVDS/HCSL/CML-capable; independently configured frequency, format, voltage, and phase.
CLK1A / CLK1B	Differential Output Pair 1	Same configurability as CLK0; supports integer/fractional synthesis and spread spectrum.
CLK2A / CLK2B	Differential Output Pair 2	Programmable drive strength and slew rate; supports loss-of-lock detection feedback path.
CLK3A / CLK3B	Differential Output Pair 3	Configurable as primary or backup clock; supports external feedback for zero-delay mode.
IN1 / IN2	Differential Reference Input 1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled.
IN3 / IN4	Single-Ended Reference Inputs	CMOS/SSTL/HSTL-compatible; supports 5–350 MHz with programmable input thresholds.
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.5/1.8/2.5/3.3 V rails per output pair; enables mixed-voltage system interfacing.
SCL / SDA	I²C Serial Interface	Standard two-wire bus (400 kHz max); used for register configuration and status readback.
INTR	Interrupt Output	Open-drain signal indicating loss-of-lock, loss-of-signal, or programmable alarm conditions.

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent fractional-N synthesizers enable simultaneous generation of unrelated frequencies (e.g., 100 MHz PCIe + 125 MHz Ethernet + 156.25 MHz SerDes + 200 MHz processor clock) with 0 ppm accuracy.
PCIe Gen 4 SRNS Compliance	0.11–0.32 ps RMS jitter in Separate Reference No Spread mode; validated per PCI-SIG Base Spec 4.0 rev 0.5 using Intel Clock Jitter Tool.
Per-Output Voltage & Format Control	Each of four output drivers supports independent selection among LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL with dedicated 1.5–3.3 V supply pin.
Glitchless Frequency Adjustment	Hardware-supported frequency increment/decrement via PINC/FDEC pins enables real-time 1 ppm step tuning without output interruption.
Programmable Phase Offset	±45 ns initial phase offset per output with <20 ps step resolution; critical for skew-sensitive applications like DDR memory interfaces.
Spread Spectrum Modulation	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate; reduces EMI in dense PCB layouts.

Applications

PCIe Gen 4 Switch Fabric	Ethernet 10GbE Line Card
Use Scenario: High-density server switch ASIC requiring synchronized 100 MHz common clock and 100.001 MHz SRNS reference for multiple PCIe Gen 4 lanes. IC Role / Device Role / Timing Role: Quad-output clock generator providing PCIe Common Clock and Separate Reference signals with sub-0.32 ps RMS jitter compliance. Use Value: Eliminates need for four discrete oscillators; enables single-chip timing solution meeting PCI-SIG jitter mask requirements across all lanes.	Use Scenario: Carrier-grade 10GbE line card with XAUI/SGMII interfaces, MAC, PHY, and packet processor requiring multiple synchronous clocks. IC Role / Device Role / Timing Role: Programmable clock source generating 156.25 MHz (XAUI), 125 MHz (SGMII), 250 MHz (PHY), and 312.5 MHz (SerDes) from one crystal reference. Use Value: Reduces BOM count and board area; supports field-upgradable clock configurations via I²C without hardware change.
FPGA-Based Broadcast Video Router	Telecom MSAN/DSLAM Timing Module
Use Scenario: SMPTE ST 2082-1 compliant 12G-SDI video router using FPGA fabric for frame synchronization and routing logic. IC Role / Device Role / Timing Role: Low-jitter clock generator delivering 27 MHz (SDI), 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) with precise phase alignment. Use Value: Enables deterministic inter-FPGA clock distribution; meets SMPTE jitter limits (<0.2 UI) for broadcast-grade video transport.	Use Scenario: Multi-service access node aggregating DSL, PON, and TDM traffic with strict ITU-T G.8262 EEC-2 wander and jitter requirements. IC Role / Device Role / Timing Role: Primary timing IC providing 1.544 MHz (T1), 2.048 MHz (E1), 155.52 MHz (SONET OC-3), and 622.08 MHz (OC-12) from a single 20 MHz TCXO. Use Value: Replaces legacy PLL+VCXO solutions; achieves <1 ps RMS jitter on SONET outputs and meets G.8262 Class C holdover stability.

PCIe Gen 4 Switch Fabric

Ethernet 10GbE Line Card

Use Scenario: High-density server switch ASIC requiring synchronized 100 MHz common clock and 100.001 MHz SRNS reference for multiple PCIe Gen 4 lanes.

IC Role / Device Role / Timing Role: Quad-output clock generator providing PCIe Common Clock and Separate Reference signals with sub-0.32 ps RMS jitter compliance.

Use Value: Eliminates need for four discrete oscillators; enables single-chip timing solution meeting PCI-SIG jitter mask requirements across all lanes.

Use Scenario: Carrier-grade 10GbE line card with XAUI/SGMII interfaces, MAC, PHY, and packet processor requiring multiple synchronous clocks.

IC Role / Device Role / Timing Role: Programmable clock source generating 156.25 MHz (XAUI), 125 MHz (SGMII), 250 MHz (PHY), and 312.5 MHz (SerDes) from one crystal reference.

Use Value: Reduces BOM count and board area; supports field-upgradable clock configurations via I²C without hardware change.

FPGA-Based Broadcast Video Router

Telecom MSAN/DSLAM Timing Module

Use Scenario: SMPTE ST 2082-1 compliant 12G-SDI video router using FPGA fabric for frame synchronization and routing logic.

IC Role / Device Role / Timing Role: Low-jitter clock generator delivering 27 MHz (SDI), 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) with precise phase alignment.

Use Value: Enables deterministic inter-FPGA clock distribution; meets SMPTE jitter limits (<0.2 UI) for broadcast-grade video transport.

Use Scenario: Multi-service access node aggregating DSL, PON, and TDM traffic with strict ITU-T G.8262 EEC-2 wander and jitter requirements.

IC Role / Device Role / Timing Role: Primary timing IC providing 1.544 MHz (T1), 2.048 MHz (E1), 155.52 MHz (SONET OC-3), and 622.08 MHz (OC-12) from a single 20 MHz TCXO.

Use Value: Replaces legacy PLL+VCXO solutions; achieves <1 ps RMS jitter on SONET outputs and meets G.8262 Class C holdover stability.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B04183-GMR	Same pinout and register map; differs only in factory-programmed NVM configuration (A vs B variant), with B variant preconfigured for specific frequency plan.	Identical use cases; A variant requires full ClockBuilder Pro configuration, while B variant ships with preloaded settings for faster bring-up.	Select SI5338B-B04183-GMR when preprogrammed configuration matching target system clock tree is required; A variant offers full flexibility.
LMK04832ISQE/NOPB	Two-stage jitter cleaner architecture (PLL + dual-loop); higher power (120 mA), larger 7×7 mm 48-VQFN package; supports JESD204B deterministic latency.	Better suited for RF sampling and JESD204B converter timing where sub-100 fs additive jitter and deterministic delay are mandatory.	Choose LMK04832ISQE/NOPB only if additive jitter <0.15 ps RMS or JESD204B SYSREF synchronization is required; SI5338B-B04183-GMR is optimal for cost- and size-sensitive PCIe/Ethernet systems.

Compared with Si5338A-B04183-GMR, the SI5338B-B04183-GMR delivers identical electrical performance with factory-loaded configuration for reduced firmware bring-up time; versus LMK04832ISQE/NOPB, it trades ultra-low additive jitter for smaller footprint, lower power, and simpler I²C-only programming-ideal for infrastructure timing where PCIe Gen 4 and 10GbE jitter compliance is primary.

Availability

SI5338B-B04183-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch fabrics, 10GbE line cards, and FPGA-based broadcast video routers requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338B-B04183-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed as a highly integrated, software-programmable clock generator family targeting high-speed digital systems requiring flexible, low-jitter timing with minimal board space-especially in networking, data center, and broadcast equipment.

FAQ

What is the default factory configuration of the SI5338B-B04183-GMR?

The SI5338B-B04183-GMR ships with non-volatile memory (NVM) preprogrammed for a specific frequency plan defined by Skyworks' B-variant configuration. Unlike the A-variant, it powers up with valid clocks on all four outputs without requiring I²C initialization-enabling immediate operation in systems where boot-time clock availability is critical. This configuration is fixed and cannot be overwritten without reprogramming via ClockBuilder Pro.

Does the SI5338B-B04183-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338B-B04183-GMR is validated for PCIe Gen 4 SRNS operation with 0.11–0.32 ps RMS jitter (typ/max) when configured with PLL bandwidth of 2–4 MHz and CDR = 10 MHz, per PCI-SIG Base Specification 4.0 rev 0.5. This performance is measured using the Skyworks PCIe Clock Jitter Tool and confirmed in Table 12 of the official datasheet.

Can the SI5338B-B04183-GMR generate four different frequencies simultaneously?

Yes, the SI5338B-B04183-GMR uses four independent MultiSynth™ fractional-N synthesizers to generate four fully unrelated output frequencies-for example, 100 MHz (PCIe), 125 MHz (Ethernet), 156.25 MHz (XAUI), and 200 MHz (FPGA core)-all from a single 25 MHz crystal reference, with 0 ppm frequency accuracy and <20 ps phase step resolution.

What is the maximum output frequency supported by the SI5338B-B04183-GMR in LVPECL format?

The SI5338B-B04183-GMR supports LVPECL output frequencies up to 710 MHz, as specified in Table 6 of the datasheet. This capability applies when operating in integer synthesis mode and using appropriate layout practices (e.g., controlled impedance, proper termination, and minimized stub length) to maintain signal integrity and jitter performance.

How does the SI5338B-B04183-GMR handle loss-of-signal detection?

The SI5338B-B04183-GMR provides dedicated loss-of-signal (LOS) detection on all six reference inputs (IN1–IN6) with programmable thresholds. Detection time is 2.6–5 µs (typ/max), and the condition triggers the open-drain INTR pin. LOS status is readable via I²C register 0x000C, enabling rapid system-level fault response without external monitoring circuitry.

SI5338B-B04183-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338B-B04183-GMR FAQ

1.How can I place an order for SI5338B-B04183-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338B-B04183-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338B-B04183-GMR reliable?

The price and inventory of SI5338B-B04183-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B04183-GMR is usually 5 days.

3.What payment methods are accepted for SI5338B-B04183-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B04183-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338B-B04183-GMR?

SI5338B-B04183-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338B-B04183-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338B-B04183-GMR?

For technical support, including SI5338B-B04183-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B04183-GMR requirements.

6.How does Aetrix verify that SI5338B-B04183-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338B-B04183-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B04183-GMR meets industry standards.

7.What is the process for return or replacement of SI5338B-B04183-GMR?

All SI5338B-B04183-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B04183-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338B-B04183-GMR part is unused and in its original packaging.

Return procedure for SI5338B-B04183-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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