Skyworks Solutions Inc. SI5338B-B04802-GMR

Overview

SI5338B-B04802-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router, FPGA clocking, and PCIe timing systems.

For engineers reviewing the SI5338B-B04802-GMR datasheet, SI5338B-B04802-GMR pinout, SI5338B-B04802-GMR application, or SI5338B-B04802-GMR equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis down to 0.16 MHz, spread-spectrum control (0.5–5.0% at 33–63 kHz), and glitchless 1 ppm frequency increment/decrement.

Technical Context

The SI5338B-B04802-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its input supports eight reference sources - external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz).

Each output driver supports independent signal format selection, voltage supply (VDDOx = 1.5/1.8/2.5/3.3 V), phase offset (±45 ns in <20 ps steps), and spread-spectrum modulation. The device uses on-chip OTP memory for factory programming and supports real-time I²C/SMBus reconfiguration without interrupting output clocks.

Key Specifications

Pinout & Package

SI5338B-B04802-GMR is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad. Pin numbering follows standard top-view layout with IN1–IN6, CLK0A–CLK3B, VDD, VDDO0–VDDO3, SCL/SDA/INTR, and reserved ground pins.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338A-B04802-GMR, the SI5338B-B04802-GMR delivers pre-validated PCIe Gen 4 timing performance without configuration overhead; versus LMK04832ISQE/NOPB, it offers lower cost, smaller footprint, and integrated crystal drive - making it optimal for volume PCIe, Ethernet, and FPGA clocking where jitter <0.45 ps RMS suffices.

Availability

SI5338B-B04802-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, Ethernet switch/router clock distribution, and FPGA/ASIC clocking requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338B-B04802-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed for high-density, multi-protocol clock generation in networking, computing, and broadcast equipment - emphasizing low jitter, flexible output formatting, and I²C programmability without external loop filters.

FAQ

What is the primary function of the SI5338B-B04802-GMR in a PCIe Gen 4 system?

The SI5338B-B04802-GMR serves as a Common Clock timing source for PCIe Gen 4 endpoints, delivering four low-jitter 100 MHz clocks compliant with the SRNS specification (<0.32 ps RMS). Its factory-programmed configuration ensures immediate interoperability with Intel and AMD root complexes without requiring ClockBuilder Pro setup, and its independent output drivers allow per-slot clock enable/disable and phase tuning to meet link training timing windows.

Does the SI5338B-B04802-GMR support spread-spectrum clocking, and how is it configured?

Yes, the SI5338B-B04802-GMR supports fully programmable spread-spectrum clocking on any output: spread range (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread only) are set via I²C registers. Configuration is validated in ClockBuilder Pro and stored in on-chip OTP; no external components are needed. This feature reduces electromagnetic interference in dense PCB layouts without compromising timing margin.

Can the SI5338B-B04802-GMR generate different output voltages on each channel?

Yes, the SI5338B-B04802-GMR provides independent VDDO0–VDDO3 supplies, allowing each of its four output drivers to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage FPGAs (e.g., LVDS banks at 2.5 V and HCSL SerDes at 1.8 V) without external level shifters, reducing signal integrity risk and board area.

What reference inputs does the SI5338B-B04802-GMR accept, and which is recommended for lowest jitter?

The SI5338B-B04802-GMR accepts crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) references. For lowest jitter, a low-phase-noise 25 MHz fundamental-mode crystal directly connected to IN1/IN2 is recommended - achieving 0.7 ps RMS typical phase jitter. Differential inputs yield ~30% lower additive jitter than single-ended due to common-mode noise rejection.

How does the SI5338B-B04802-GMR handle loss-of-signal or loss-of-lock conditions?

The SI5338B-B04802-GMR monitors all input references and PLL lock status continuously. Upon detecting loss-of-signal (within 2.6–5 µs) or loss-of-lock (within 5–10 ms), it asserts the open-drain INTR pin. This signal can trigger system-level failover, such as switching to a backup clock or initiating reset sequences. Debounce time and response behavior are configurable via I²C registers.