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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338B-B04857-GM

Name: SI5338B-B04857-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338B-B04857-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338B-B04857-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338B-B04857-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338B-B04857-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.

For engineers reviewing the SI5338B-B04857-GM datasheet, SI5338B-B04857-GM pinout, SI5338B-B04857-GM application, or SI5338B-B04857-GM equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-pin 4×4 mm QFN package with I²C/SMBus interface.

Technical Context

The SI5338B-B04857-GM implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating outputs with true zero-ppm accuracy. Each output path includes programmable phase offset (<20 ps step), frequency increment/decrement (1 ppm steps), and spread-spectrum modulation (33–63 kHz rate).

It supports flexible clock buffering (PLL bypass mode) with additive phase jitter as low as 0.165 ps RMS (12 kHz–20 MHz), loss-of-lock and loss-of-signal alarms, and external feedback for zero-delay operation. Core supply operates at 1.8/2.5/3.3 V with 45 mA typical current draw at 100 MHz on all outputs and 25 MHz reference.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 independent outputs; configurable as LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL/CML
Frequency range per output	0.16–710 MHz (LVPECL/LVDS); 0.16–250 MHz (HCSL); 0.16–350 MHz (SSTL/HSTL)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), compliant with PCIe Gen 3 SRNS and GbE standards
Input reference options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating temperature	–40 to +85 °C ambient, qualified per industrial requirements

Pinout & Package

SI5338B-B04857-GM uses a 24-pin 4×4 mm QFN package with exposed thermal pad (pin 24 = GND). Pin assignments are fixed per Si5338 family: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref 2), IN5/IN6 (differential ref 3), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential reference input 1	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3, IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); VIH/VIL referenced to VDD
CLK0A, CLK0B – CLK3A, CLK3B	Differential clock outputs	Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CML with dedicated VDDOx
VDDO0 – VDDO3	Output buffer supply rails	Enable per-output voltage selection (1.5/1.8/2.5/3.3 V) for mixed-signal system interfacing
SCL, SDA	I²C/SMBus interface	Standard 2-wire serial bus (up to 400 kHz) for configuration and status monitoring
INTR	Interrupt output	Open-drain signal indicating loss-of-lock, loss-of-signal, or other fault conditions

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables independent, any-frequency generation (0.16–710 MHz) on all four outputs with 0 ppm precision
PCIe Gen 1–4 compliance	Meets Common Clock and Gen 3 SRNS jitter specs (≤0.32 ps RMS), validated using Intel Clock Jitter Tool
Independent phase control	Programmable initial phase offset (±45 ns) and fine-grained adjustment (<20 ps step) per output
Spread-spectrum clocking	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI
Flexible reference inputs	Supports six distinct input types - crystal, CMOS, SSTL, HSTL, and two differential pairs - enabling multi-source timing architectures

Applications

Ethernet Switch/Router Timing	PCIe Gen 3/4 Clocking
Use Scenario: High-density 1/10 GbE switching fabric requiring synchronous, low-jitter clocks for SERDES lanes and packet processing units. IC Role / Device Role / Timing Role: Primary clock generator providing four independent 125 MHz, 156.25 MHz, and 312.5 MHz outputs with matched skew and sub-1 ps RMS jitter. Use Value: Eliminates need for multiple discrete oscillators; enables deterministic latency via programmable phase alignment across PHY and MAC domains.	Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, CPU interconnect, and NVMe storage controllers. IC Role / Device Role / Timing Role: Common clock source delivering 100 MHz PCIe REFCLK to all endpoints with Gen 4-compliant jitter (≤0.45 ps RMS). Use Value: Ensures PCIe link training success and long-term reliability by meeting SRNS jitter mask without external filtering or reclocking.
Broadcast Video/Audio Sync	FPGA & Processor Clocking
Use Scenario: SMPTE 2110 IP video router requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with frame-accurate phase relationships. IC Role / Device Role / Timing Role: Multi-format clock synthesizer generating LVDS and HCSL outputs simultaneously at broadcast-grade jitter performance. Use Value: Maintains lip-sync and color fidelity across distributed video streams by eliminating accumulated timing drift between sources.	Use Scenario: Industrial embedded controller with Xilinx Zynq SoC, DDR4 memory, Gigabit Ethernet PHY, and ADC/DAC interfaces. IC Role / Device Role / Timing Role: Central timing hub supplying 300 MHz PS clock, 200 MHz DDR4 clock, 125 MHz GMII clock, and 10 MHz debug clock from a single crystal reference. Use Value: Reduces BOM count and PCB area while enabling dynamic frequency scaling and glitchless transitions via I²C-controlled PDEC/FDEC pins.

Ethernet Switch/Router Timing

PCIe Gen 3/4 Clocking

Use Scenario: High-density 1/10 GbE switching fabric requiring synchronous, low-jitter clocks for SERDES lanes and packet processing units.

IC Role / Device Role / Timing Role: Primary clock generator providing four independent 125 MHz, 156.25 MHz, and 312.5 MHz outputs with matched skew and sub-1 ps RMS jitter.

Use Value: Eliminates need for multiple discrete oscillators; enables deterministic latency via programmable phase alignment across PHY and MAC domains.

Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, CPU interconnect, and NVMe storage controllers.

IC Role / Device Role / Timing Role: Common clock source delivering 100 MHz PCIe REFCLK to all endpoints with Gen 4-compliant jitter (≤0.45 ps RMS).

Use Value: Ensures PCIe link training success and long-term reliability by meeting SRNS jitter mask without external filtering or reclocking.

Broadcast Video/Audio Sync

FPGA & Processor Clocking

Use Scenario: SMPTE 2110 IP video router requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with frame-accurate phase relationships.

IC Role / Device Role / Timing Role: Multi-format clock synthesizer generating LVDS and HCSL outputs simultaneously at broadcast-grade jitter performance.

Use Value: Maintains lip-sync and color fidelity across distributed video streams by eliminating accumulated timing drift between sources.

Use Scenario: Industrial embedded controller with Xilinx Zynq SoC, DDR4 memory, Gigabit Ethernet PHY, and ADC/DAC interfaces.

IC Role / Device Role / Timing Role: Central timing hub supplying 300 MHz PS clock, 200 MHz DDR4 clock, 125 MHz GMII clock, and 10 MHz debug clock from a single crystal reference.

Use Value: Reduces BOM count and PCB area while enabling dynamic frequency scaling and glitchless transitions via I²C-controlled PDEC/FDEC pins.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B04857-GM	Same pinout and register map; differs only in factory-programmed NVM configuration (A vs B variant)	Identical use cases; B variant includes preloaded configuration optimized for PCIe Gen 4 common clock mode	Select SI5338B-B04857-GM when PCIe Gen 4 SRNS compliance is required out-of-box; A variant requires full ClockBuilder Pro reconfiguration
LMK04832RHAR	Two PLLs + 14 outputs; higher power (95 mA), larger 48-pin WQFN; no integrated crystal driver	Better suited for ultra-low-jitter (<0.1 ps RMS) RF or test equipment; over-specified for standard server/switch timing	Choose LMK04832RHAR only if >10 outputs or sub-0.2 ps RMS jitter is mandatory; SI5338B-B04857-GM offers superior cost, size, and ease-of-use for mainstream compute/comm

Compared with Si5338A-B04857-GM, the SI5338B-B04857-GM delivers immediate PCIe Gen 4 readiness without software configuration; versus LMK04832RHAR, it reduces board space by 58%, cuts core power by 53%, and eliminates need for external loop filter components.

Availability

SI5338B-B04857-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 4 clocking, and FPGA-based industrial control systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338B-B04857-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with broad portfolio certification for automotive, industrial, and communications markets.

The Si5338 product line was designed specifically for high-density, multi-protocol timing consolidation in networking, data center, and broadcast equipment - enabling replacement of multiple oscillators with a single programmable, low-jitter clock generator.

FAQ

What is the default factory configuration of the SI5338B-B04857-GM?

The SI5338B-B04857-GM ships with a pre-programmed OTP configuration optimized for PCIe Gen 4 Common Clock operation: 100 MHz LVDS outputs on CLK0A/B and CLK1A/B, 100 MHz HCSL on CLK2A/B, and 100 MHz LVDS on CLK3A/B, all synchronized to a 25 MHz crystal input. This eliminates boot-time I²C programming for PCIe applications.

Does the SI5338B-B04857-GM support spread-spectrum clocking on all four outputs simultaneously?

Yes, the SI5338B-B04857-GM supports independent spread-spectrum modulation on any or all outputs. Each output can be configured with unique spread percentage (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread only), enabling targeted EMI reduction across multiple subsystems without cross-coupling.

Can the SI5338B-B04857-GM generate frequencies above 350 MHz on more than two outputs?

No. Per the Si5338 datasheet (Table 6, Note 6), only two unique frequencies above 350 MHz may be generated simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints. All four outputs can operate above 350 MHz only if they share one of those two frequencies.

What is the minimum input slew rate required for optimal jitter performance on differential inputs?

For optimal jitter performance on differential inputs (IN1/IN2, IN5/IN6), the SI5338B-B04857-GM requires a midpoint differential input slew rate faster than 0.3 V/ns, as specified in Table 6 Notes 2 and 7. Slower slew rates increase deterministic jitter and degrade PCIe/GbE compliance margins.

How does the SI5338B-B04857-GM handle loss-of-signal detection during operation?

The SI5338B-B04857-GM provides hardware-level loss-of-signal (LOS) detection on all six input pins (IN1–IN6) with programmable thresholds. Detection time is 2.6–5 µs (tLOS), and release time is 0.01–1 µs (tLOSRLS). An interrupt (INTR pin) asserts within 10 ms of lock loss, enabling rapid system failover or diagnostic logging.

SI5338B-B04857-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338B-B04857-GM FAQ

1.How can I place an order for SI5338B-B04857-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338B-B04857-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338B-B04857-GM reliable?

The price and inventory of SI5338B-B04857-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B04857-GM is usually 5 days.

3.What payment methods are accepted for SI5338B-B04857-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B04857-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338B-B04857-GM?

SI5338B-B04857-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338B-B04857-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338B-B04857-GM?

For technical support, including SI5338B-B04857-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B04857-GM requirements.

6.How does Aetrix verify that SI5338B-B04857-GM is sourced from the original manufacturer or authorized distributors?

All SI5338B-B04857-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B04857-GM meets industry standards.

7.What is the process for return or replacement of SI5338B-B04857-GM?

All SI5338B-B04857-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B04857-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338B-B04857-GM part is unused and in its original packaging.

Return procedure for SI5338B-B04857-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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