Skyworks Solutions Inc. SI5338B-B04871-GM
- Part No.:
- SI5338B-B04871-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338B-B04871-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338B-B04871-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output. It delivers four independent differential or single-ended clocks (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) across 0.16–710 MHz, supports PCIe Gen 1–4 common clock and SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package for FPGA, processor, and switch/router timing applications.
For engineers reviewing the SI5338B-B04871-GM datasheet, SI5338B-B04871-GM pinout, SI5338B-B04871-GM application, or SI5338B-B04871-GM equivalent, key selection considerations include its 0.7 ps RMS typical phase jitter, independent per-output voltage (1.5–3.3 V), flexible reference inputs (crystal, CMOS, SSTL, differential), glitchless 1 ppm frequency increment/decrement, and <20 ps phase step resolution - all configurable via I²C or ClockBuilder Pro software.
Technical Context
The SI5338B-B04871-GM integrates a two-stage PLL architecture: a high-performance integer-N PLL (Stage 1) locks to one of six input references (IN1–IN6), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output with sub-ppb resolution. Its output stage supports mixed-signal formats and per-driver supply voltage control (VDDO0–VDDO3).
It features loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, programmable spread spectrum (0.5–5.0% spread, 33–63 kHz modulation), and independent phase/frequency adjustment on all four outputs - enabling dynamic clock tuning without glitches in real-time systems like PCIe root complexes and broadcast video synchronizers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3/4 SRNS and GbE jitter requirements |
| Output Frequency Range | 0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 & Fvco/6) |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Output Format Flexibility | LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL per driver; independent VDDO (1.5/1.8/2.5/3.3 V) |
| Frequency Resolution | 1 ppb synthesis resolution; true zero ppm accuracy on all outputs in integer mode |
| Core Supply Current | 45 mA typical at 100 MHz on all outputs and 25 MHz refclk; low-power operation |
| Operating Temperature | –40 °C to +85 °C; qualified for industrial and telecom line card environments |
Pinout & Package
SI5338B-B04871-GM is housed in a 4 × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family: six input pins (IN1–IN6), eight clock output terminals (CLK0A/B through CLK3A/B), four VDDO supplies (VDDO0–VDDO3), dual core VDD, SCL/SDA/I²C interface, INTR alarm, and reserved ground.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential clock input pairs | Accept 5–710 MHz AC-coupled differential signals; require external 100 Ω termination |
| IN3, IN4 | Single-ended clock inputs | Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; DC-coupled with internal bias |
| CLK0A/CLK0B – CLK3A/CLK3B | Differential clock outputs | Four independent LVPECL/LVDS/HCSL/CML outputs; each pair shares VDDOx supply |
| VDDO0–VDDO3 | Output buffer supply rails | Enable per-output voltage selection (1.5/1.8/2.5/3.3 V) for mixed-voltage system interfacing |
| SCL, SDA | I²C/SMBus interface | Standard 100 kHz / 400 kHz / 1 MHz serial programming; supports ClockBuilder Pro configuration |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock or loss-of-signal events |
Key Features
| Feature | Design Value |
|---|---|
| Independent per-output frequency synthesis | Four MultiSynth™ engines enable simultaneous, unrelated frequencies (e.g., 100 MHz PCIe + 125 MHz Ethernet + 148.5 MHz video + 1 GHz FPGA core) |
| Glitchless frequency tuning | 1 ppm step size with pin-controlled or I²C-initiated increment/decrement; no output interruption during reconfiguration |
| Programmable phase alignment | <20 ps step resolution and ±45 ns range per output; enables precise skew management across multi-lane interfaces |
| PCIe Gen 3/4 SRNS compliance | 0.11–0.45 ps RMS jitter in Separate Reference No Spread mode; validated per PCI-SIG specification |
| Flexible spread spectrum | Configurable 0.5–5.0% down-spread at 33–63 kHz on any output; reduces EMI without affecting timing margins |
Applications
| PCIe Gen 4 Root Complex | Ethernet Switch Timing |
|---|---|
Use Scenario: Providing synchronized 100 MHz common clock and 100 MHz reference clock to CPU, GPU, and PCIe endpoint devices in a server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering PCIe Gen 4-compliant common clock (CLK0A/B) and SRNS reference (CLK1A/B) with <0.45 ps RMS jitter. Use Value: Eliminates need for multiple discrete oscillators; ensures deterministic latency and meets PCIe Base Spec 4.0 jitter mask. |
Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and MAC layers in a modular switch fabric. IC Role / Device Role / Timing Role: Configurable clock source supporting mixed-rate Ethernet standards with independent format and voltage per port. Use Value: Enables single-chip support for legacy and next-gen Ethernet PHYs; reduces BOM count and layout complexity. |
| Broadcast Video Synchronizer | FPGA-Based Test Equipment |
Use Scenario: Delivering genlock-accurate 27 MHz, 74.25 MHz, and 148.5 MHz clocks to SDI transmitters, video processors, and frame synchronizers in broadcast infrastructure. IC Role / Device Role / Timing Role: Precision clock generator with <20 ps phase step resolution and zero ppm synthesis for SMPTE ST 2059-2 PTP traceability. Use Value: Enables frame-accurate multi-camera switching and eliminates timing drift between distributed video nodes. |
Use Scenario: Providing programmable, low-jitter clocks to high-speed ADC/DAC, memory controllers, and logic analyzers in automated test equipment. IC Role / Device Role / Timing Role: Reconfigurable clock source supporting variable sampling rates (e.g., 125 MHz → 250 MHz → 500 MHz) via I²C during test sequence execution. Use Value: Enables dynamic clock rate changes without hardware modification; improves test coverage and reduces calibration overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B04871-GM | Same pinout and register map; differs only in factory-programmed NVM configuration (A vs B variant) | Identical functional capability; B variant includes pre-loaded configuration for specific customer use case | Select SI5338B-B04871-GM when factory-tuned initialization is required; A variant requires full ClockBuilder Pro configuration |
| LMK04832RHAR | Two PLLs + eight outputs; higher power (120 mA), larger 7 × 7 mm package; supports JESD204B deterministic latency | Better suited for RF/data converter timing with sub-ps jitter and deterministic delay; not drop-in compatible | Choose LMK04832RHAR only when JESD204B sync, ultra-low additive jitter (<0.1 ps), or >4 outputs are mandatory |
Compared with Si5338A-B04871-GM, the SI5338B-B04871-GM offers identical electrical performance but ships with pre-programmed OTP settings for faster time-to-operation; versus LMK04832RHAR, it provides lower cost, smaller footprint, and adequate jitter for PCIe/Ethernet, but lacks JESD204B support and deterministic latency features.
Availability
SI5338B-B04871-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, 10/25 GbE switch designs, and broadcast video synchronizers requiring stable component supply, long-term lifecycle assurance, and consistent factory-programmed configuration.
Supply support for SI5338B-B04871-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line was designed to replace multiple crystal oscillators with a single, software-configurable clock generator for high-speed digital systems - targeting PCIe, Ethernet, broadcast, and FPGA-based applications demanding low jitter, flexible output formats, and rapid design iteration.
FAQ
What is the factory-programmed configuration of SI5338B-B04871-GM?
The SI5338B-B04871-GM is pre-programmed with a specific clock tree configuration stored in one-time-programmable (OTP) memory. This includes defined input reference selection, output frequencies (e.g., 100 MHz, 125 MHz, 156.25 MHz), signal formats (LVDS), and VDDO voltages. Unlike the 'A' variant, the 'B' variant boots directly into this configuration without requiring I²C initialization - reducing boot time and simplifying firmware integration for the SI5338B-B04871-GM.
Does SI5338B-B04871-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
Yes, the SI5338B-B04871-GM supports PCIe Gen 4 SRNS mode with 0.15–0.45 ps RMS jitter (typ/max) when configured with a 2–5 MHz PLL bandwidth and CDR = 10 MHz. This compliance is verified per PCI-SIG Base Specification 4.0 rev. 0.5 using HCSL 100 MHz outputs. The SI5338B-B04871-GM achieves this via its low-noise MultiSynth™ architecture and optimized loop filter settings accessible through ClockBuilder Pro.
Can SI5338B-B04871-GM generate three outputs above 350 MHz simultaneously?
No. The SI5338B-B04871-GM can generate only two unique frequencies above 350 MHz simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints and synthesis stage limitations. Attempting to configure three outputs >350 MHz will result in invalid frequency combinations or failure to lock. Valid high-frequency combinations must be verified using ClockBuilder Pro before finalizing the SI5338B-B04871-GM design.
What is the minimum input slew rate required for optimal jitter performance on SI5338B-B04871-GM?
For optimal jitter performance, the SI5338B-B04871-GM requires ≥0.3 V/ns differential input slew rate on IN1/IN2/IN5/IN6 and ≥1.0 V/ns single-ended slew rate on IN3/IN4. These thresholds ensure clean edge transitions into the phase detector, minimizing deterministic jitter contributions. Measured 0.7 ps RMS phase jitter assumes these slew rate conditions are met - falling below them may increase measured jitter beyond specification for the SI5338B-B04871-GM.
How does the independent VDDO supply per output benefit system design with SI5338B-B04871-GM?
The SI5338B-B04871-GM's independent VDDO0–VDDO3 rails allow each output driver to operate at different supply voltages (1.5/1.8/2.5/3.3 V), enabling direct interface with mixed-voltage ICs - e.g., 1.8 V LVDS to an FPGA bank, 3.3 V CMOS to a microcontroller, and 2.5 V HCSL to a PHY - without level shifters. This reduces component count, PCB area, and signal integrity risk while maintaining specified jitter and drive strength for each SI5338B-B04871-GM output path.
SI5338B-B04871-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338B-B04871-GM FAQ
1.How can I place an order for SI5338B-B04871-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338B-B04871-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338B-B04871-GM reliable?
The price and inventory of SI5338B-B04871-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B04871-GM is usually 5 days.
3.What payment methods are accepted for SI5338B-B04871-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B04871-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338B-B04871-GM?
SI5338B-B04871-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338B-B04871-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338B-B04871-GM?
For technical support, including SI5338B-B04871-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B04871-GM requirements.
6.How does Aetrix verify that SI5338B-B04871-GM is sourced from the original manufacturer or authorized distributors?
All SI5338B-B04871-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B04871-GM meets industry standards.
7.What is the process for return or replacement of SI5338B-B04871-GM?
All SI5338B-B04871-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B04871-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338B-B04871-GM part is unused and in its original packaging.
Return procedure for SI5338B-B04871-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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