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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338B-B04872-GMR

Name: SI5338B-B04872-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338B-B04872-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338B-B04872-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338B-B04872-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338B-B04872-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL outputs up to 710 MHz. It replaces up to four discrete oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338B-B04872-GMR datasheet, SI5338B-B04872-GMR pinout, SI5338B-B04872-GMR application, or SI5338B-B04872-GMR equivalent, key selection criteria include differential output jitter performance at PCIe Gen 4, independent per-output voltage (1.5/1.8/2.5/3.3 V), spread-spectrum modulation configurability (0.5–5.0% down-spread), and 24-QFN package compatibility with space-constrained FPGA/ASIC clock trees.

Technical Context

The SI5338B-B04872-GMR integrates a dual-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Input flexibility includes crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) references.

Each of the four differential output pairs (CLK0A/B through CLK3A/B) supports independent format selection, voltage rail assignment (VDDO0–VDDO3), phase offset (±45 ns), and frequency increment/decrement (1 ppm steps, <20 ps phase step accuracy). Loss-of-lock and loss-of-signal alarms are provided via the INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	Four differential output pairs (CLK0A/B–CLK3A/B); supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL
Frequency range	0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), compliant with PCIe Gen 4 common clock and OC-12 requirements
Supply voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom line card environments
I²C interface	SMBus-compatible, 100 kHz / 400 kHz standard/fast mode; supports ClockBuilder Pro configuration

Pinout & Package

SI5338B-B04872-GMR is housed in a 24-lead, 4 mm × 4 mm QFN package with wettable flank leads and an exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND), and pin 12 is center-bottom (INTR).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pair	Accepts 5–710 MHz AC-coupled differential clocks; requires external 100 Ω termination
IN3, IN4	Single-ended input	Supports 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B (x4 pairs)	Differential clock outputs	Configurable format/voltage per pair; each pair shares one VDDOx supply rail
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output group; decoupling required per rail
VDD	Core supply	1.8/2.5/3.3 V core; PSRR optimized; 45 mA typical current at 100 MHz on all outputs
SCL, SDA	I²C control interface	Standard two-wire bus; supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling true zero-ppm frequency accuracy on all outputs simultaneously
PCIe Gen 4 compliance	0.15–0.45 ps RMS jitter in common clock mode; meets PCIe Base Spec 4.0 rev 0.5 jitter limits
Per-output spread spectrum	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI
Glitchless frequency tuning	Independent frequency increment/decrement via pin or I²C with 1 ppm step size and <667 ns update time
Programmable phase offset	±45 ns adjustment per output with <20 ps step resolution for skew compensation in multi-lane interfaces
Flexible input reference	Supports crystal (8–30 MHz), single-ended (5–200 MHz), and differential (5–710 MHz) inputs without external components

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized, low-jitter reference clocks to a 32-lane PCIe Gen 4 switch ASIC with separate clocks for SerDes lanes, management logic, and PHY interface. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, jitter-clean clocks - two at 100 MHz (HCSL) for SerDes, one at 25 MHz (LVDS) for management, one at 156.25 MHz (LVDS) for PHY. Use Value: Meets PCIe Gen 4 common clock TJ < 33.6 ps pk-pk and RMS jitter < 0.45 ps, eliminating need for multiple discrete oscillators and reducing board area by >60%.	Use Scenario: Generating precise, low-phase-noise clocks for a 10 GbE/25 GbE Ethernet switch fabric with integrated MAC/PHY and packet buffer controllers. IC Role / Device Role / Timing Role: Configured as free-running generator with 156.25 MHz (LVDS), 312.5 MHz (LVDS), 125 MHz (HCSL), and 25 MHz (CMOS) outputs for SERDES, PCS, buffer memory, and management subsystems. Use Value: Achieves 0.7 ps RMS jitter across all outputs, satisfying IEEE 802.3bj/802.3by jitter budgets and enabling reliable 25 GbE KR/KR4 link training.
FPGA-Based Broadcast Video System	Telecom Line Card Synchronization
Use Scenario: Delivering frame-synchronized pixel clocks, audio sample clocks, and genlock references in a 4K/8K broadcast video processing platform using Xilinx Versal FPGA. IC Role / Device Role / Timing Role: Four-output generator providing 148.5 MHz (LVDS) for HDMI TX, 297 MHz (LVDS) for DP 1.4, 48 kHz (CMOS) for audio codec, and 10 MHz (LVDS) for GPS-disciplined genlock. Use Value: Independent phase adjustment (±45 ns, <20 ps steps) enables sub-pixel timing alignment across video pipelines, critical for SMPTE ST 2110-10/20 compliance.	Use Scenario: Serving as primary timing source in a carrier-grade telecom line card requiring synchronization to SyncE and IEEE 1588 PTP grandmaster clocks. IC Role / Device Role / Timing Role: Accepts 19.44 MHz OC-12 reference (SSTL) and generates 155.52 MHz (LVDS), 622.08 MHz (LVPECL), 2.048 MHz (CMOS), and 10 MHz (LVDS) outputs for SONET/SDH, OTN, TDM, and management interfaces. Use Value: 0.7 ps RMS jitter satisfies ITU-T G.823/G.8262 wander and jitter masks; loss-of-signal detection ensures fast failover to backup timing sources.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized, low-jitter reference clocks to a 32-lane PCIe Gen 4 switch ASIC with separate clocks for SerDes lanes, management logic, and PHY interface.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, jitter-clean clocks - two at 100 MHz (HCSL) for SerDes, one at 25 MHz (LVDS) for management, one at 156.25 MHz (LVDS) for PHY.

Use Value: Meets PCIe Gen 4 common clock TJ < 33.6 ps pk-pk and RMS jitter < 0.45 ps, eliminating need for multiple discrete oscillators and reducing board area by >60%.

Use Scenario: Generating precise, low-phase-noise clocks for a 10 GbE/25 GbE Ethernet switch fabric with integrated MAC/PHY and packet buffer controllers.

IC Role / Device Role / Timing Role: Configured as free-running generator with 156.25 MHz (LVDS), 312.5 MHz (LVDS), 125 MHz (HCSL), and 25 MHz (CMOS) outputs for SERDES, PCS, buffer memory, and management subsystems.

Use Value: Achieves 0.7 ps RMS jitter across all outputs, satisfying IEEE 802.3bj/802.3by jitter budgets and enabling reliable 25 GbE KR/KR4 link training.

FPGA-Based Broadcast Video System

Telecom Line Card Synchronization

Use Scenario: Delivering frame-synchronized pixel clocks, audio sample clocks, and genlock references in a 4K/8K broadcast video processing platform using Xilinx Versal FPGA.

IC Role / Device Role / Timing Role: Four-output generator providing 148.5 MHz (LVDS) for HDMI TX, 297 MHz (LVDS) for DP 1.4, 48 kHz (CMOS) for audio codec, and 10 MHz (LVDS) for GPS-disciplined genlock.

Use Value: Independent phase adjustment (±45 ns, <20 ps steps) enables sub-pixel timing alignment across video pipelines, critical for SMPTE ST 2110-10/20 compliance.

Use Scenario: Serving as primary timing source in a carrier-grade telecom line card requiring synchronization to SyncE and IEEE 1588 PTP grandmaster clocks.

IC Role / Device Role / Timing Role: Accepts 19.44 MHz OC-12 reference (SSTL) and generates 155.52 MHz (LVDS), 622.08 MHz (LVPECL), 2.048 MHz (CMOS), and 10 MHz (LVDS) outputs for SONET/SDH, OTN, TDM, and management interfaces.

Use Value: 0.7 ps RMS jitter satisfies ITU-T G.823/G.8262 wander and jitter masks; loss-of-signal detection ensures fast failover to backup timing sources.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B04872-GMR	Same pinout and register map; differs only in factory-programmed NVM configuration (A vs B variant)	Pre-configured for different default output frequencies and formats; not interchangeable without reprogramming	Select based on pre-loaded configuration - SI5338B-B04872-GMR delivers factory-tuned settings for PCIe Gen 4 reference clocking
LMK04832RHAR	Two PLLs (not four independent synthesizers); higher power (120 mA core); larger 48-QFN package	Targeted at JESD204B/C converter timing with deterministic latency; less suited for multi-protocol clock translation	Choose LMK04832RHAR only when deterministic delay, dual-loop redundancy, or ultra-low additive jitter (<0.1 ps) are required over per-output flexibility

Compared with Si5338A-B04872-GMR, the SI5338B-B04872-GMR offers identical hardware but factory-optimized firmware for PCIe Gen 4 timing; versus LMK04832RHAR, it provides greater output format independence and lower footprint at the cost of deterministic latency control.

Availability

SI5338B-B04872-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch design, 10/25 GbE switch timing, and broadcast video FPGA clocking requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338B-B04872-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets, with leadership in RF, timing, and power management ICs.

The Si5338 family was designed as a highly configurable, low-jitter clock generator platform for high-speed serial interface timing in datacenter switches, telecom line cards, and broadcast video systems - emphasizing flexibility, integration, and PCIe/SONET/IEEE 1588 compliance.

FAQ

What is the factory-programmed configuration of the SI5338B-B04872-GMR?

The SI5338B-B04872-GMR ships with non-volatile memory (NVM) pre-programmed for PCIe Gen 4 common clock operation: outputs configured as 100 MHz HCSL (CLK0), 100 MHz HCSL (CLK1), 100 MHz HCSL (CLK2), and 25 MHz LVDS (CLK3), with PLL bandwidth set to 2–4 MHz and spread-spectrum disabled. This eliminates initial configuration effort for PCIe switch designs.

Does the SI5338B-B04872-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338B-B04872-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical) when configured with PLL bandwidth of 2–4 MHz and CDR = 10 MHz. Its MultiSynth™ architecture allows independent output tuning to meet SRNS requirements without external components.

Can the SI5338B-B04872-GMR generate four different output frequencies simultaneously?

Yes, the SI5338B-B04872-GMR synthesizes four independent frequencies simultaneously - e.g., 156.25 MHz, 312.5 MHz, 125 MHz, and 25 MHz - using its four MultiSynth™ engines. Each output supports integer or fractional synthesis with 1 ppb resolution and zero ppm cumulative error.

What is the maximum differential output frequency supported by the SI5338B-B04872-GMR?

The SI5338B-B04872-GMR supports differential output frequencies up to 710 MHz for LVPECL/LVDS/CML and up to 250 MHz for HCSL. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) due to VCO constraints.

How is spread-spectrum clocking configured on the SI5338B-B04872-GMR?

Spread-spectrum clocking on the SI5338B-B04872-GMR is configured per output via I²C registers: spread percentage (0.5–5.0% down-spread), modulation rate (33–63 kHz), and center-spread or down-spread mode. Default is 0.5% down-spread at ~31.5 kHz, enabled via ClockBuilder Pro or direct register write.

SI5338B-B04872-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338B-B04872-GMR FAQ

1.How can I place an order for SI5338B-B04872-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338B-B04872-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338B-B04872-GMR reliable?

The price and inventory of SI5338B-B04872-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B04872-GMR is usually 5 days.

3.What payment methods are accepted for SI5338B-B04872-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B04872-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338B-B04872-GMR?

SI5338B-B04872-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338B-B04872-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338B-B04872-GMR?

For technical support, including SI5338B-B04872-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B04872-GMR requirements.

6.How does Aetrix verify that SI5338B-B04872-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338B-B04872-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B04872-GMR meets industry standards.

7.What is the process for return or replacement of SI5338B-B04872-GMR?

All SI5338B-B04872-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B04872-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338B-B04872-GMR part is unused and in its original packaging.

Return procedure for SI5338B-B04872-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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