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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338B-B04973-GM

Name: SI5338B-B04973-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338B-B04973-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338B-B04973-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338B-B04973-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338B-B04973-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in FPGA, processor, and Ethernet switch timing systems.

For engineers reviewing the SI5338B-B04973-GM datasheet, SI5338B-B04973-GM pinout, SI5338B-B04973-GM application, or SI5338B-B04973-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% down-spread), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338B-B04973-GM implements a two-stage PLL architecture: a high-stability reference stage (with programmable R-divider) feeding a wideband VCO, followed by four independent MultiSynth™ fractional-N synthesis blocks per output. Each output supports integer or fractional mode with <20 ps programmable phase step accuracy and glitchless frequency increment/decrement in 1 ppm steps.

Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references. Output drivers support LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats across 0.16–710 MHz, with independent VDDO per channel and internal 22 Ω series termination for differential outputs.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS).
Output Count & Type	Four independent outputs: up to 4 differential (LVPECL/LVDS/HCSL/CML) or 8 single-ended (CMOS/SSTL/HSTL), or mixed.
Frequency Range	0.16–710 MHz per output; supports >350 MHz on two outputs simultaneously (Fvco/4 and Fvco/6).
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, –40 to +85 °C operating range.
Control Interface	I²C/SMBus-compatible serial interface; programmable via ClockBuilder Pro software.

Pinout & Package

SI5338B-B04973-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family: IN1/IN2 (diff input 1), IN3/IN4 (SE input), IN5/IN6 (diff input 2), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C bus), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	LVPECL/LVDS/HCSL/CML-capable; independently configured frequency, format, and VDDO0 voltage.
CLK1A / CLK1B	Differential Output Pair 1	Same configurability as CLK0; supports integer/fractional synthesis and <20 ps phase adjustment.
CLK2A / CLK2B	Differential Output Pair 2	Independent MultiSynth™ block; enables simultaneous PCIe Gen 4 (100 MHz) and 156.25 MHz Ethernet clocks.
CLK3A / CLK3B	Differential Output Pair 3	Supports HCSL up to 250 MHz or LVDS up to 350 MHz; usable for FPGA reference or SerDes clocking.
VDDO0–VDDO3	Output Buffer Supply	Each powers one output pair; allows mixed-voltage system interfacing (e.g., 1.8 V FPGA + 3.3 V legacy logic).
SCL / SDA	I²C Serial Interface	Standard bidirectional bus; supports configuration, status readback, and real-time frequency tuning.
INTR	Interrupt Output	Open-drain signal asserting loss-of-lock or loss-of-signal; enables system-level fault monitoring without polling.
IN1/IN2, IN5/IN6	Differential Reference Inputs	Accept 5–710 MHz AC-coupled signals; internal 10 kΩ termination and 3.5 pF capacitance.
IN3 / IN4	Single-Ended Reference Inputs	Support CMOS/SSTL/HSTL; 5–350 MHz range; 2–4 pF input capacitance; 20 kΩ pull-up/down resistance.

Key Features

Feature	Design Value
MultiSynth™ Synthesis	Four independent fractional-N synthesizers enabling true zero-ppm frequency accuracy on all outputs with 1 ppb resolution.
PCIe Gen 4 Compliance	Meets Common Clock jitter spec (0.15–0.45 ps RMS) and SRNS requirements without external filtering or layout constraints.
Glitchless Frequency Tuning	Hardware-supported 1 ppm step frequency increment/decrement via dedicated pins (PINC/FDEC), eliminating output interruptions during dynamic reconfiguration.
Programmable Spread Spectrum	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI in dense PCB layouts.
Zero-Delay Mode	External feedback path enables synchronous clock distribution with matched input-to-output propagation delay (2.5–4 ns typical).

Applications

PCIe Gen 4 Server Backplane	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe Gen 4 slots and root complex in a 1U server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks meeting PCIe Gen 4 CEM v5.0 jitter mask. Use Value: Eliminates need for four discrete oscillators; reduces BOM count and board area while guaranteeing 0.15–0.45 ps RMS jitter compliance.	Use Scenario: Generating 156.25 MHz SerDes reference, 125 MHz PHY clock, 25 MHz management interface, and 10 MHz test clock in a 10 GbE line card. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer supporting mixed-format outputs (LVDS, HCSL, CMOS) from a single 25 MHz crystal. Use Value: Enables single-crystal design with independent voltage domains (1.8 V FPGA, 3.3 V PHY), reducing power supply complexity and jitter coupling.
FPGA-Based Video Processing	Telecom Line Card Synchronization
Use Scenario: Driving high-speed transceivers (e.g., Xilinx GTY), DDR4 memory controller, video pixel clock (148.5 MHz), and AXI interconnect in broadcast-grade video encoder. IC Role / Device Role / Timing Role: Configurable quad clock source with sub-20 ps phase step control for skew alignment across data paths. Use Value: Achieves deterministic inter-clock phase relationships required for SMPTE ST 2082-1 12G-SDI compliance without manual trace-length matching.	Use Scenario: Delivering stratum-3 compliant 2.048 MHz, 19.44 MHz, 155.52 MHz, and 622.08 MHz clocks to T1/E1 framers, SONET/SDH PHYs, and packet processors in a carrier-grade line card. IC Role / Device Role / Timing Role: High-stability frequency translator accepting OC-12 reference and generating telecom-standard rates with <1 ps RMS additive jitter. Use Value: Replaces discrete PLL+VCXO solutions; maintains holdover stability during reference loss via internal NVM configuration storage.

PCIe Gen 4 Server Backplane

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe Gen 4 slots and root complex in a 1U server motherboard.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks meeting PCIe Gen 4 CEM v5.0 jitter mask.

Use Value: Eliminates need for four discrete oscillators; reduces BOM count and board area while guaranteeing 0.15–0.45 ps RMS jitter compliance.

Use Scenario: Generating 156.25 MHz SerDes reference, 125 MHz PHY clock, 25 MHz management interface, and 10 MHz test clock in a 10 GbE line card.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer supporting mixed-format outputs (LVDS, HCSL, CMOS) from a single 25 MHz crystal.

Use Value: Enables single-crystal design with independent voltage domains (1.8 V FPGA, 3.3 V PHY), reducing power supply complexity and jitter coupling.

FPGA-Based Video Processing

Telecom Line Card Synchronization

Use Scenario: Driving high-speed transceivers (e.g., Xilinx GTY), DDR4 memory controller, video pixel clock (148.5 MHz), and AXI interconnect in broadcast-grade video encoder.

IC Role / Device Role / Timing Role: Configurable quad clock source with sub-20 ps phase step control for skew alignment across data paths.

Use Value: Achieves deterministic inter-clock phase relationships required for SMPTE ST 2082-1 12G-SDI compliance without manual trace-length matching.

Use Scenario: Delivering stratum-3 compliant 2.048 MHz, 19.44 MHz, 155.52 MHz, and 622.08 MHz clocks to T1/E1 framers, SONET/SDH PHYs, and packet processors in a carrier-grade line card.

IC Role / Device Role / Timing Role: High-stability frequency translator accepting OC-12 reference and generating telecom-standard rates with <1 ps RMS additive jitter.

Use Value: Replaces discrete PLL+VCXO solutions; maintains holdover stability during reference loss via internal NVM configuration storage.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-A05639-GM	Higher integration: integrated crystal option, lower jitter (0.35 ps RMS), supports up to 10 outputs, but requires different programming flow and larger 5 × 5 mm package.	Better suited for new designs requiring ultra-low jitter and crystal integration; not drop-in compatible due to pinout and register map differences.	Select when PCIe Gen 5 readiness or integrated reference is required; avoid for cost-sensitive or space-constrained retrofits.
ICS853S02AGT	Fixed-function dual-output LVDS clock generator; no I²C programmability, no fractional synthesis, max 700 MHz output, higher jitter (1.2 ps RMS).	Limited to static clock trees; cannot replace four oscillators or support dynamic frequency changes.	Use only in simple, low-cost applications where frequency agility and multi-format support are unnecessary.

Compared with Si5332A-A05639-GM and ICS853S02AGT, the SI5338B-B04973-GM delivers optimal balance of programmability, PCIe Gen 4 compliance, and compact 4 × 4 mm footprint-making it ideal for field-upgradable timing in space-constrained server, networking, and telecom platforms where four independent, low-jitter clocks are required.

Availability

SI5338B-B04973-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server backplanes, 10 GbE switch timing, and FPGA-based video processing requiring stable component supply, long-term lifecycle support, and guaranteed RoHS-compliant manufacturing.

Supply support for SI5338B-B04973-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed specifically for high-performance, software-configurable clock generation in data center, networking, and telecom infrastructure-enabling consolidation of multiple oscillators into a single, PCIe- and Ethernet-compliant timing IC.

FAQ

What is the maximum output frequency supported by the SI5338B-B04973-GM?

The SI5338B-B04973-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6), as defined by the VCO architecture. All outputs maintain 0.7 ps RMS typical jitter within their respective format limits.

Does the SI5338B-B04973-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338B-B04973-GM is explicitly validated for PCIe Gen 4 Common Clock compliance with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz band) using 100 MHz HCSL outputs and a PLL bandwidth of 2–5 MHz. This meets the PCI-SIG Base Specification 4.0 rev. 0.5 requirement without external filtering or layout modifications.

Can the SI5338B-B04973-GM generate different output voltages on each channel?

Yes, the SI5338B-B04973-GM provides independent VDDO0–VDDO3 supply pins, allowing each of its four output pairs to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage systems-for example, driving a 1.8 V FPGA transceiver bank and a 3.3 V legacy microcontroller from the same device.

How is the SI5338B-B04973-GM programmed and configured?

The SI5338B-B04973-GM is programmed via its I²C/SMBus-compatible serial interface using Skyworks' ClockBuilder Pro software. Configuration includes frequency, format, voltage, spread spectrum, phase offset, and alarm thresholds. Pre-programmed devices boot with factory settings; field updates require I²C write access and nonvolatile memory (OTP) programming.

What reference inputs does the SI5338B-B04973-GM accept?

The SI5338B-B04973-GM accepts four types of reference inputs: external crystal (8–30 MHz), single-ended CMOS (5–200 MHz), single-ended SSTL/HSTL (5–350 MHz), and differential (5–710 MHz). Input pins IN1/IN2 and IN5/IN6 support AC-coupled differential clocks; IN3/IN4 support DC-coupled single-ended signals with programmable termination.

SI5338B-B04973-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338B-B04973-GM FAQ

1.How can I place an order for SI5338B-B04973-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338B-B04973-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338B-B04973-GM reliable?

The price and inventory of SI5338B-B04973-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B04973-GM is usually 5 days.

3.What payment methods are accepted for SI5338B-B04973-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B04973-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338B-B04973-GM?

SI5338B-B04973-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338B-B04973-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338B-B04973-GM?

For technical support, including SI5338B-B04973-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B04973-GM requirements.

6.How does Aetrix verify that SI5338B-B04973-GM is sourced from the original manufacturer or authorized distributors?

All SI5338B-B04973-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B04973-GM meets industry standards.

7.What is the process for return or replacement of SI5338B-B04973-GM?

All SI5338B-B04973-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B04973-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338B-B04973-GM part is unused and in its original packaging.

Return procedure for SI5338B-B04973-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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