Skyworks Solutions Inc. SI5338B-B04973-GMR

Overview

SI5338B-B04973-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz), supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, achieves 0.7 ps RMS phase jitter, and operates from 1.8/2.5/3.3 V core supply in PCIe Gen 1–4 timing systems.

For engineers reviewing the SI5338B-B04973-GMR datasheet, SI5338B-B04973-GMR pinout, SI5338B-B04973-GMR application, or SI5338B-B04973-GMR equivalent, this page provides verified technical context, pin-level design meaning, PCIe-compliant jitter performance, and validated alternative options for multi-protocol clocking designs.

Technical Context

The SI5338B-B04973-GMR integrates a dual-stage PLL architecture: a high-bandwidth (1.6 MHz) Phase-Locked Loop (PLL) for reference locking and a fractional-N MultiSynth™ stage per output for independent frequency synthesis. Each output driver supports programmable voltage (1.5–3.3 V), format, and phase offset (<20 ps resolution).

It accepts flexible references - 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential - and enables glitchless frequency adjustment in 1 ppm steps via dedicated control pins or I²C. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring.

Key Specifications

Pinout & Package

SI5338B-B04973-GMR is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments are defined per Skyworks Rev. 1.6 datasheet (page 33), with dedicated input, output, power, and control terminals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5338A-B04973-GM, SI5338B-B04973-GMR offers identical hardware but distinct factory OTP settings; compared with LMK04832RHAT, it trades output count and JESD204B support for smaller footprint and lower power - ideal for PCIe/Ethernet clock consolidation where four outputs suffice.

Availability

SI5338B-B04973-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch synchronization, and broadcast video frame sync requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338B-B04973-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed digital systems - designed specifically to replace multiple fixed-frequency oscillators while meeting stringent PCIe, Ethernet, and telecom timing standards.

FAQ

What is the primary function of the SI5338B-B04973-GMR in a PCIe Gen 4 system?

The SI5338B-B04973-GMR serves as a quad-output clock generator delivering four synchronized 100 MHz PCIe Gen 4 common clocks with ≤0.45 ps RMS jitter. It replaces up to four discrete oscillators, supports loss-of-lock monitoring via INTR, and meets PCIe Gen 4 common clock jitter specifications per the Base Specification 4.0 rev. 0.5. Its MultiSynth™ engine ensures zero-ppm frequency accuracy across all outputs.

Does the SI5338B-B04973-GMR support spread spectrum clocking (SSC), and how is it configured?

Yes, the SI5338B-B04973-GMR supports spread spectrum clocking on any output with programmable spread (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread only). Configuration is performed via I²C registers or ClockBuilder Pro software; no external components are required. Default settings apply 0.5% down-spread at ~31.5 kHz, and SSC can be enabled/disabled per output independently.

How does the SI5338B-B04973-GMR handle different output voltage levels and signal formats simultaneously?

The SI5338B-B04973-GMR supports independent VDDO supplies (VDDO0–VDDO3) per output pair, enabling simultaneous 1.8 V LVDS, 2.5 V HCSL, and 3.3 V CMOS outputs. Each output driver is individually configurable for LVPECL, LVDS, HCSL, CML, CMOS, SSTL, or HSTL format via register settings. This eliminates external level shifters and simplifies mixed-voltage system clocking.

Can the SI5338B-B04973-GMR operate in clock buffer (PLL bypass) mode, and what are its jitter characteristics in that mode?

Yes, the SI5338B-B04973-GMR supports clock buffer mode with PLL bypass, achieving additive phase jitter of 0.165 ps RMS (12 kHz–20 MHz) and 0.225 ps RMS (50 kHz–80 MHz) for a 622.08 MHz differential input. In this mode, propagation delay is 2.5–4 ns, and outputs mirror the input clock with minimal added jitter - ideal for low-latency fanout or jitter-sensitive instrumentation paths.

What reference inputs does the SI5338B-B04973-GMR accept, and are external components required?

The SI5338B-B04973-GMR accepts 8–30 MHz crystals (with internal load capacitance tuning), 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential references. For differential inputs (IN1/IN2, IN5/IN6), an external 100 Ω termination resistor is required. Crystal inputs need no external load caps due to on-chip programmable capacitance (11–13 pF supported, 17–19 pF recommended).