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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338B-B05287-GM

Name: SI5338B-B05287-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338B-B05287-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338B-B05287-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338B-B05287-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338B-B05287-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338B-B05287-GM datasheet, SI5338B-B05287-GM pinout, SI5338B-B05287-GM application, or SI5338B-B05287-GM equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis capability (0.16–710 MHz), and PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS).

Technical Context

The SI5338B-B05287-GM implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each MultiSynth supports integer or fractional mode with <20 ps programmable phase step resolution and 1 ppm frequency increment/decrement.

Input reference options include external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz). Output drivers support independent voltage selection (1.5/1.8/2.5/3.3 V), spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate), and loss-of-lock/loss-of-signal alarms via INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS).
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz).
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz); six input pins (IN1–IN6).
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; output buffers: 1.4–3.63 V independently configurable per driver (VDDO0–VDDO3).
Package & Size	24-pin QFN, 4 × 4 mm footprint, 0.5 mm pitch; RoHS-compliant, –40 to +85 °C operating range.
Interface & Control	I²C/SMBus-compatible serial interface (SCL/SDA); INTR pin for loss-of-lock/loss-of-signal status; OEB/PINC/FDEC pins for hardware control.

Pinout & Package

SI5338B-B05287-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed across Si5338 family variants.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential Input Pair	Accepts AC-coupled differential reference clocks (5–710 MHz); requires external 100 Ω termination.
IN3, IN4	Single-Ended Input	Supports CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD.
CLK0A, CLK0B – CLK3A, CLK3B	Differential Output Pairs	Four independent differential outputs; each pair supports LVPECL/LVDS/HCSL/CML with per-driver VDDO voltage setting.
VDDO0–VDDO3	Output Buffer Supply	Independent 1.4–3.63 V supplies per output bank; sets logic level and drive strength.
VDD	Core Supply	1.8/2.5/3.3 V ±10% core power; PSRR optimized for low-noise clock generation.
SCL, SDA	I²C Interface	Standard I²C bus (up to 400 kHz) for configuration; supports ClockBuilder Pro programming.
INTR	Interrupt Output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) events.
OEB, PINC, FDEC	Hardware Control	Output enable (active-low), phase increment/decrement, frequency increment/decrement pins for real-time dynamic adjustment.

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent outputs with true zero-ppm accuracy across 0.16–710 MHz; eliminates need for multiple crystals.
PCIe Gen 4 Common Clock Compliance	0.15–0.45 ps RMS jitter (10 kHz–50 MHz band); validated per PCI Express Base Spec 4.0 rev. 0.5.
Flexible Output Configuration	Per-output format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage (1.5–3.3 V), and slew rate control.
Glitchless Dynamic Adjustment	Hardware-controlled phase/frequency tuning in <20 ps steps and 1 ppm increments without output interruption.
Spread Spectrum Clocking (SSC)	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate, enabling EMI reduction.

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in data center top-of-rack switches. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with SRNS support. Use Value: Enables deterministic latency and link training stability across 16+ lanes while reducing board space versus discrete oscillators.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and SerDes in carrier-grade Ethernet routers. IC Role / Device Role / Timing Role: Programmable frequency translator converting a single 25 MHz crystal into multiple Ethernet-standard frequencies. Use Value: Eliminates clock tree complexity and jitter accumulation from cascaded buffers; supports IEEE 802.3bj/802.3by jitter specs.
Broadcast Video Timing	FPGA/Processor Clocking
Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 742.5 MHz and ST 2081 (6G-SDI) 371.25 MHz clocks to video encoder/decoder FPGAs in broadcast production switchers. IC Role / Device Role / Timing Role: High-frequency differential clock source with sub-ps jitter for multi-gigabit serial video interfaces. Use Value: Meets SMPTE ST 2082 jitter mask (≤0.3 UI pk-pk) at 742.5 MHz using LVPECL outputs with optimized layout.	Use Scenario: Supplying core, DDR, and peripheral clocks (e.g., 100 MHz, 200 MHz, 300 MHz) to Xilinx Versal or Intel Agilex FPGAs in AI inference accelerators. IC Role / Device Role / Timing Role: Configurable quad clock generator supporting mixed-voltage FPGA banks (1.0 V core, 1.8 V I/O, 3.3 V peripherals). Use Value: Reduces BOM count and PCB layer count by consolidating clocks; enables dynamic reconfiguration via I²C during system boot.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in data center top-of-rack switches.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with SRNS support.

Use Value: Enables deterministic latency and link training stability across 16+ lanes while reducing board space versus discrete oscillators.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and SerDes in carrier-grade Ethernet routers.

IC Role / Device Role / Timing Role: Programmable frequency translator converting a single 25 MHz crystal into multiple Ethernet-standard frequencies.

Use Value: Eliminates clock tree complexity and jitter accumulation from cascaded buffers; supports IEEE 802.3bj/802.3by jitter specs.

Broadcast Video Timing

FPGA/Processor Clocking

Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 742.5 MHz and ST 2081 (6G-SDI) 371.25 MHz clocks to video encoder/decoder FPGAs in broadcast production switchers.

IC Role / Device Role / Timing Role: High-frequency differential clock source with sub-ps jitter for multi-gigabit serial video interfaces.

Use Value: Meets SMPTE ST 2082 jitter mask (≤0.3 UI pk-pk) at 742.5 MHz using LVPECL outputs with optimized layout.

Use Scenario: Supplying core, DDR, and peripheral clocks (e.g., 100 MHz, 200 MHz, 300 MHz) to Xilinx Versal or Intel Agilex FPGAs in AI inference accelerators.

IC Role / Device Role / Timing Role: Configurable quad clock generator supporting mixed-voltage FPGA banks (1.0 V core, 1.8 V I/O, 3.3 V peripherals).

Use Value: Reduces BOM count and PCB layer count by consolidating clocks; enables dynamic reconfiguration via I²C during system boot.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05287-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), but larger 32-QFN (5 × 5 mm) package.	Required for systems needing >4 outputs or tighter jitter budgets (e.g., 5G wireless fronthaul).	Select when additional outputs or sub-0.5 ps jitter are mandatory; SI5338B-B05287-GM remains optimal for cost- and space-constrained 4-output designs.
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS clock generator; no I²C interface; higher jitter (1.2 ps RMS).	Suitable only for static clock trees where frequencies never change post-manufacture.	Choose only if design requires zero firmware dependency and all clocks are fixed; SI5338B-B05287-GM provides field-upgradable timing flexibility.

Compared with Si5332A-D05287-GM and ICS8430I-01T, the SI5338B-B05287-GM delivers optimal balance of programmability, jitter performance (0.7 ps RMS), and compact 4 × 4 mm footprint-making it ideal for PCIe Gen 4, Ethernet, and broadcast video systems requiring four precisely controlled clocks without layout or BOM overhead.

Availability

SI5338B-B05287-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch/router clocking, and broadcast video/audio timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338B-B05287-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family is engineered for high-performance, multi-protocol timing in datacenter, telecom, and broadcast systems-delivering programmable any-frequency synthesis with ultra-low jitter in minimal footprint.

FAQ

What is the maximum output frequency supported by the SI5338B-B05287-GM in LVPECL mode?

The SI5338B-B05287-GM supports LVPECL outputs up to 710 MHz. This is confirmed in Table 6 of the datasheet under "Output Clocks (Differential)" for LVPECL/LVDS/CML formats. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6), and requires careful layout to maintain signal integrity and jitter performance.

Does the SI5338B-B05287-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338B-B05287-GM is explicitly compliant with PCIe Gen 3 SRNS and Gen 4 Common Clock specifications. Table 12 lists "PCIe Gen 3 Separate Reference No Spread, SRNS" with 0.11–0.32 ps RMS jitter and "PCIe Gen 4, Common Clock" with 0.15–0.45 ps RMS jitter, both measured using Intel Clock Jitter Tool v1.6.4 per PCI Express Base Spec 4.0 rev. 0.5.

Can the SI5338B-B05287-GM generate four different output frequencies simultaneously?

Yes, the SI5338B-B05287-GM uses four independent MultiSynth™ engines to synthesize four distinct frequencies simultaneously-from 0.16 MHz to 710 MHz-with zero ppm error. Each output is fully configurable for format, voltage, and phase offset, enabling true multi-protocol clocking (e.g., 100 MHz PCIe, 125 MHz Ethernet, 156.25 MHz SerDes, 312.5 MHz FPGA).

What input reference options does the SI5338B-B05287-GM support?

The SI5338B-B05287-GM accepts six input references: differential (IN1/IN2, IN5/IN6; 5–710 MHz), single-ended CMOS (IN3/IN4; 5–200 MHz), SSTL/HSTL (IN3/IN4; 5–350 MHz), or an external crystal (8–30 MHz on IN1/IN2). All inputs are selectable via register configuration, enabling flexible system-level clock tree design.

Is ClockBuilder Pro software required to configure the SI5338B-B05287-GM?

No-ClockBuilder Pro is optional but strongly recommended. The SI5338B-B05287-GM is configured via standard I²C/SMBus commands (SCL/SDA), allowing full customization through embedded firmware. ClockBuilder Pro simplifies register setup, jitter simulation, and configuration file generation, but direct register writes are fully supported per the Si5338 Register Map (Rev. 1.6, Section 6).

SI5338B-B05287-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338B-B05287-GM FAQ

1.How can I place an order for SI5338B-B05287-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338B-B05287-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338B-B05287-GM reliable?

The price and inventory of SI5338B-B05287-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B05287-GM is usually 5 days.

3.What payment methods are accepted for SI5338B-B05287-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B05287-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338B-B05287-GM?

SI5338B-B05287-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338B-B05287-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338B-B05287-GM?

For technical support, including SI5338B-B05287-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B05287-GM requirements.

6.How does Aetrix verify that SI5338B-B05287-GM is sourced from the original manufacturer or authorized distributors?

All SI5338B-B05287-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B05287-GM meets industry standards.

7.What is the process for return or replacement of SI5338B-B05287-GM?

All SI5338B-B05287-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B05287-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338B-B05287-GM part is unused and in its original packaging.

Return procedure for SI5338B-B05287-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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