Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338B-B05287-GMR

Name: SI5338B-B05287-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338B-B05287-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338B-B05287-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338B-B05287-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,478

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338B-B05287-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router, processor/FPGA clocking, and broadcast video timing systems.

For engineers reviewing the SI5338B-B05287-GMR datasheet, SI5338B-B05287-GMR pinout, SI5338B-B05287-GMR application, or SI5338B-B05287-GMR equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5–3.3 V), spread-spectrum capability (0.5–5.0% spread, 33–63 kHz modulation), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338B-B05287-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its input stage accepts differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or 8–30 MHz crystal references.

Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage rails (VDDO0–VDDO3), programmable phase offset (±45 ns, <20 ps step), and glitchless frequency increment/decrement (1 ppm steps). External feedback mode enables zero-delay operation, and status monitoring includes INTR pin assertion for loss-of-lock and loss-of-signal events.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements at 125 MHz output
Output Frequency Range	0.16–710 MHz - supports integer/fractional synthesis across all four outputs simultaneously
Input Reference Options	8–30 MHz crystal, 5–710 MHz differential, 5–350 MHz SSTL/HSTL - enables flexible system clock sourcing
Output Format Support	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - allows direct interface to FPGAs, processors, SerDes, and memory controllers
Supply Voltages	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - supports mixed-voltage board designs with independent output rail control
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm - space-efficient footprint compatible with automated SMT assembly

Pinout & Package

SI5338B-B05287-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential Input Pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-Ended Input Pins	Support 5–200 MHz CMOS inputs; VIH/VIL referenced to VDD; internal 20 kΩ pull-up/down resistors
CLK0A/CLK0B – CLK3A/CLK3B	Differential Output Pairs	Four independent output drivers; each configurable for LVPECL/LVDS/HCSL/CML with dedicated VDDOx supply
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.4–3.63 V rails per output pair - enable mixed-signal voltage domain interfacing
SCL/SDA	I²C Interface	Standard SMBus-compatible 100/400 kHz interface; supports write-only configuration and read-back of status registers
INTR	Interrupt Output	Open-drain active-low signal indicating loss-of-lock, loss-of-signal, or NVM programming completion
VDD	Core Supply	1.8/2.5/3.3 V ±10% core power; typical IDD = 45 mA at 100 MHz on all outputs with 25 MHz refclk
GND / RSVD_GND	Ground Connections	Eight ground pins including dedicated thermal pad connection - ensure low-impedance return path for jitter-sensitive clock paths

Key Features

Feature	Design Value
MultiSynth™ Synthesis	Four independent fractional-N synthesizers enabling true zero-ppm accuracy on any output frequency between 0.16–710 MHz
PCIe Compliance	Fully compliant with PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS specifications - validated using Intel Clock Jitter Tool
Spread Spectrum Control	Per-output programmable SSC: 0.5–5.0% spread depth, 33–63 kHz modulation rate - reduces EMI without affecting timing margins
Glitchless Frequency Tuning	Pin-controlled or I²C-based frequency increment/decrement in 1 ppm steps - enables dynamic clock scaling without output interruption
Phase Adjustment	Independent ±45 ns phase offset per output with <20 ps resolution - supports precise skew alignment in multi-lane SerDes systems
Alarm Monitoring	Hardware-level loss-of-lock and loss-of-signal detection with interrupt assertion on INTR pin - enables real-time system health monitoring

Applications

Processor and FPGA Clocking	PCIe Gen 1–4 Timing
Use Scenario: Providing multiple synchronized clock domains to heterogeneous SoCs, ASICs, and Xilinx/Intel FPGAs in embedded computing and AI accelerator platforms. IC Role / Device Role / Timing Role: Quad-output clock generator delivering independent, low-jitter clocks for core logic, DDR interfaces, PCIe root complexes, and peripheral buses. Use Value: Eliminates need for discrete oscillators and fanout buffers; enables dynamic frequency scaling via I²C or pin control while maintaining sub-1 ps RMS jitter.	Use Scenario: Generating compliant reference clocks for PCIe Gen 1–4 endpoints and switches in servers, storage controllers, and NICs. IC Role / Device Role / Timing Role: Common Clock architecture generator meeting PCIe Gen 3 SRNS and Gen 4 jitter limits (0.11–0.45 ps RMS) with integrated spread spectrum. Use Value: Passes PCIe compliance testing without external jitter cleaners; supports both common clock and separate reference no spread (SRNS) modes.
Ethernet Switch/Routing	Broadcast Video/Audio Timing
Use Scenario: Synchronizing packet processing, MAC/PHY interfaces, and traffic management units in 1/10 GbE enterprise switches and telecom MSAN/DSLAM systems. IC Role / Device Role / Timing Role: Any-frequency clock converter generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks from a single 25 MHz crystal reference. Use Value: Reduces BOM count by replacing multiple oscillators; supports IEEE 1588 PTP grandmaster clock synchronization via precise phase control.	Use Scenario: Delivering frame-locked, low-jitter pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and audio word clocks (e.g., 48 kHz, 96 kHz) in SDI routers, IP video encoders, and broadcast production switchers. IC Role / Device Role / Timing Role: High-precision clock synthesizer with <20 ps phase step resolution for genlock and lip-sync alignment across video/audio subsystems. Use Value: Achieves SMPTE ST 2059-2 compliance; eliminates timing drift between video pipelines and audio DSPs through deterministic phase adjustment.

Processor and FPGA Clocking

PCIe Gen 1–4 Timing

Use Scenario: Providing multiple synchronized clock domains to heterogeneous SoCs, ASICs, and Xilinx/Intel FPGAs in embedded computing and AI accelerator platforms.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering independent, low-jitter clocks for core logic, DDR interfaces, PCIe root complexes, and peripheral buses.

Use Value: Eliminates need for discrete oscillators and fanout buffers; enables dynamic frequency scaling via I²C or pin control while maintaining sub-1 ps RMS jitter.

Use Scenario: Generating compliant reference clocks for PCIe Gen 1–4 endpoints and switches in servers, storage controllers, and NICs.

IC Role / Device Role / Timing Role: Common Clock architecture generator meeting PCIe Gen 3 SRNS and Gen 4 jitter limits (0.11–0.45 ps RMS) with integrated spread spectrum.

Use Value: Passes PCIe compliance testing without external jitter cleaners; supports both common clock and separate reference no spread (SRNS) modes.

Ethernet Switch/Routing

Broadcast Video/Audio Timing

Use Scenario: Synchronizing packet processing, MAC/PHY interfaces, and traffic management units in 1/10 GbE enterprise switches and telecom MSAN/DSLAM systems.

IC Role / Device Role / Timing Role: Any-frequency clock converter generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks from a single 25 MHz crystal reference.

Use Value: Reduces BOM count by replacing multiple oscillators; supports IEEE 1588 PTP grandmaster clock synchronization via precise phase control.

Use Scenario: Delivering frame-locked, low-jitter pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and audio word clocks (e.g., 48 kHz, 96 kHz) in SDI routers, IP video encoders, and broadcast production switchers.

IC Role / Device Role / Timing Role: High-precision clock synthesizer with <20 ps phase step resolution for genlock and lip-sync alignment across video/audio subsystems.

Use Value: Achieves SMPTE ST 2059-2 compliance; eliminates timing drift between video pipelines and audio DSPs through deterministic phase adjustment.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B05287-GM	Same pinout and register map; differs only in factory-programmed NVM configuration (A vs B variant); identical electrical specs and jitter performance	No functional difference in PCIe, Ethernet, or FPGA clocking use cases; both meet same JEDEC and PCIe jitter standards	Select based on preloaded configuration file - SI5338B-B05287-GMR ships with default settings optimized for general-purpose any-frequency synthesis
LMK04832ISQE/NOPB	Two-stage jitter cleaner + dual-loop PLL; higher power (120 mA typ), larger 7 × 7 mm package; supports JESD204B subclass 1 deterministic latency	Better suited for RF sampling and high-speed data converter timing where sub-100 fs additive jitter is required; not drop-in replaceable due to different pinout and power architecture	Choose LMK04832 for ultra-low additive jitter (<50 fs) in ADC/DAC clock trees; SI5338B-B05287-GMR remains optimal for cost-sensitive, space-constrained PCIe/FPGA clock generation

Compared with Si5338A-B05287-GM, SI5338B-B05287-GMR offers identical hardware functionality but with a distinct factory NVM image; compared with LMK04832ISQE/NOPB, it delivers lower power, smaller footprint, and simpler configuration at the expense of deterministic latency features needed in JESD204B systems.

Availability

SI5338B-B05287-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 endpoint timing, and broadcast video/audio timing applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338B-B05287-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 40 years of RF and precision timing expertise.

The Si5338 product line was designed specifically for high-density, multi-protocol clock generation in networking, computing, and broadcast equipment - enabling consolidation of multiple oscillators into a single programmable IC with PCIe, Ethernet, and video timing compliance.

FAQ

What is the primary function of the SI5338B-B05287-GMR in a system design?

The SI5338B-B05287-GMR serves as an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output clocks from a single input reference. It replaces up to four discrete oscillators in applications like PCIe timing, FPGA clocking, and Ethernet switching. Its MultiSynth™ technology ensures 0 ppm frequency accuracy and supports LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL output formats - making SI5338B-B05287-GMR ideal for heterogeneous system-on-module designs requiring flexible, space-efficient clock distribution.

Does the SI5338B-B05287-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338B-B05287-GMR meets PCIe Gen 4 Common Clock jitter specifications with 0.15–0.45 ps RMS (1.5 MHz–50 MHz integration band), as verified using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4. It operates in standard Common Clock mode with a PLL bandwidth of 2–4 MHz and CDR = 10 MHz. SI5338B-B05287-GMR also supports Gen 3 Separate Reference No Spread (SRNS) mode with 0.11–0.32 ps RMS jitter, satisfying strict SerDes receiver margin requirements without external jitter cleaning.

How many input reference sources can the SI5338B-B05287-GMR accept simultaneously?

The SI5338B-B05287-GMR supports up to six input clock sources: two differential pairs (IN1/IN2 and IN5/IN6), two single-ended inputs (IN3 and IN4), and one crystal oscillator (across IN1/IN2). However, only one reference is active at a time - selected via register configuration. The device does not perform automatic switchover or holdover; reference selection must be managed externally or through firmware. SI5338B-B05287-GMR's flexibility lies in supporting diverse input types (8–30 MHz crystal, 5–710 MHz differential, 5–350 MHz SSTL/HSTL) rather than concurrent multi-reference operation.

Can the SI5338B-B05287-GMR generate spread-spectrum clocking (SSC) on individual outputs?

Yes, the SI5338B-B05287-GMR provides per-output spread-spectrum clocking with fully independent control: spread depth (0.5–5.0%), modulation rate (33–63 kHz), and center-spread/down-spread mode are configurable for any output operating between 5–350 MHz. This capability reduces electromagnetic interference (EMI) in dense PCB layouts without compromising timing integrity - critical for passing FCC/CE emissions tests. SI5338B-B05287-GMR's SSC engine operates within the MultiSynth™ synthesizer stage, ensuring deterministic modulation behavior and no impact on phase jitter outside the specified spread band.

What development tools are available to configure the SI5338B-B05287-GMR?

Skyworks provides ClockBuilder Pro software - a free, GUI-based configuration tool that generates custom .cgb files for SI5338B-B05287-GMR. It supports full register mapping, jitter simulation, output format validation, and I²C script export. Users can define input references, output frequencies, formats, voltages, and SSC parameters, then simulate phase noise and jitter before programming. SI5338B-B05287-GMR also supports in-system programming via standard I²C (100/400 kHz), and Skyworks offers evaluation kits (e.g., Si5338-EVB) with USB interface and GUI for rapid prototyping and validation.

SI5338B-B05287-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338B-B05287-GMR FAQ

1.How can I place an order for SI5338B-B05287-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338B-B05287-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338B-B05287-GMR reliable?

The price and inventory of SI5338B-B05287-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338B-B05287-GMR is usually 5 days.

3.What payment methods are accepted for SI5338B-B05287-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338B-B05287-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338B-B05287-GMR?

SI5338B-B05287-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338B-B05287-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338B-B05287-GMR?

For technical support, including SI5338B-B05287-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338B-B05287-GMR requirements.

6.How does Aetrix verify that SI5338B-B05287-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338B-B05287-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338B-B05287-GMR meets industry standards.

7.What is the process for return or replacement of SI5338B-B05287-GMR?

All SI5338B-B05287-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338B-B05287-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338B-B05287-GMR part is unused and in its original packaging.

Return procedure for SI5338B-B05287-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…